Semiconductor power device and method for producing same

• US 10,515,805 B2
• Filed: 03/26/2018
• Issued: 12/24/2019
• Est. Priority Date: 02/02/2011
• Status: Active Grant

• Current Assignee: ROHM Co., Ltd.
• Original Assignee: ROHM Co., Ltd.
• Inventors: Nakano, Yuki
• Primary Examiner(s): Hossain, Moazzam
• Application Number:
  US15/935,945
• Publication Number:
  US 20180277371A1
• Time in Patent Office: 638 Days
• CPC Class Codes: H01L 21/02164 the material being a silicon oxide, e.g. SiO2
• CPC Class Codes: H01L 21/0217 the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz H01L21/02126 and H01L21/0214 take precedence
• CPC Class Codes: H01L 21/02178 the material containing aluminium, e.g. Al2O3
• CPC Class Codes: H01L 21/02241 III-V semiconductor
• CPC Class Codes: H01L 21/02255 formation by thermal treatment H01L21/02252 takes precedence; after treatment of an insulating film H01L21/3105 and subgroups
• CPC Class Codes: H01L 21/02271 deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition H01L21/02266 takes precedence
• CPC Class Codes: H01L 21/044 Conductor-insulator-semiconductor electrodes
• CPC Class Codes: H01L 21/049 Conductor-insulator-semiconductor electrodes, e.g. MIS contacts
• CPC Class Codes: H01L 21/28008 Making conductor-insulator-semiconductor electrodes
• CPC Class Codes: H01L 21/28264 the insulator being formed after the semiconductor body, the semiconductor being a III-V compound
• CPC Class Codes: H01L 2224/0603 Bonding areas having different sizes, e.g. different heights or widths
• CPC Class Codes: H01L 27/04 the substrate being a semiconductor body
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/1602 Diamond
• CPC Class Codes: H01L 29/1608 Silicon carbide
• CPC Class Codes: H01L 29/2003 Nitride compounds
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42368 : the thickness being non-uniform
• CPC Class Codes: H01L 29/513 : the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/517 : the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/518 : the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
• CPC Class Codes: H01L 29/66045 : Field-effect transistors
• CPC Class Codes: H01L 29/6606 : the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
• CPC Class Codes: H01L 29/66068 : the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
• CPC Class Codes: H01L 29/66446 : with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
• CPC Class Codes: H01L 29/7806 : the other device being a Schottky barrier diode
• CPC Class Codes: H01L 29/7811 : with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 : with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/8611 : Planar PN junction diodes
• CPC Class Codes: H01L 29/872 : Schottky diodes

Abstract

A method for producing a semiconductor power device includes forming a gate trench from a surface of the semiconductor layer toward an inside thereof. A first insulation film is formed on the inner surface of the gate trench. The method also includes removing a part on a bottom surface of the gate trench in the first insulation film. A second insulation film having a dielectric constant higher than SiO2 is formed in such a way as to cover the bottom surface of the gate trench exposed by removing the first insulation film.

Claims

1. A semiconductor device, comprising:

a semiconductor substrate having a first conductivity type;

a gate trench formed at the semiconductor substrate;

a gate insulating film formed along a side of the gate trench and a bottom surface of the gate trench, and partly covering a surface of the semiconductor substrate;

a gate electrode formed so as to be buried in the gate trench;

an interlayer insulating film formed so as to cover the gate electrode and the gate insulating film;

an intermediate stacked portion formed astride the semiconductor substrate and the interlayer insulating film;

a metal layer formed on or over the intermediate stacked portion;

a first source region having the first conductivity type formed near the side of the gate trench from a surface of the semiconductor substrate;

a first body region having a second conductivity type formed under the first source region, the first body region formed along the side of the gate trench;

a body contact region electrically connected to the first body region in a cross sectional view; and

a diode region formed at an under region lower than the first body region in a cross sectional view.

2. The semiconductor device according to claim 1, wherein the intermediate stacked portion has a layer containing Ti.

3. The semiconductor device according to claim 2, wherein the layer containing Ti is a TiN layer.

4. The semiconductor device according to claim 1, wherein the metal layer is an Al layer.

5. The semiconductor device according to claim 4, wherein a thickness of the metal layer is about 5 μ

m.

6. The semiconductor device according to claim 1, wherein a side of the gate insulating film is flush with a side of the interlayer insulating film on or over the semiconductor substrate.

7. The semiconductor device according to claim 1, wherein a plurality of the gate trenches are formed at equal intervals at a surface of the semiconductor substrate in a plan view.

8. The semiconductor device according to claim 7, further comprising a plurality of guard rings formed along an outer periphery of the semiconductor substrate at the surface of the semiconductor substrate in a plan view.

9. The semiconductor device according to claim 1, wherein the intermediate stacked portion is formed so as to have a substantially uniform thickness.

10. The semiconductor device according to claim 1, wherein the side of the gate trench is connected to the bottom surface of the gate trench via a curved surface in a cross sectional view.

11. The semiconductor device according to claim 1, wherein a length of the first source region is longer than a length of the first body region in a cross sectional view.

12. The semiconductor device according to claim 11, wherein a length of the diode region is longer than a length of the first body region in a cross sectional view.

13. The semiconductor device according to claim 12, wherein the first conductivity type is an n type and the second conductivity type is a p type.

14. The semiconductor device according to claim 1, wherein a length of the first body region is about 7.2 μ

m in a cross sectional view.

15. The semiconductor device according to claim 1, wherein a length of the body contact region is about 1.6 μ

m in a cross sectional view.

16. The semiconductor device according to claim 1, wherein a length of the first source region is about 5.7 μ

m in a cross sectional view.

17. The semiconductor device according to claim 1, wherein a plurality of the first body region are formed with an interval of about 2.8 μ

m in-between at the semiconductor substrate in a plan view.

18. The semiconductor device according to claim 1, wherein a length of the diode region is greater than or equal to 4 μ

m in a cross sectional view.

19. The semiconductor device according to claim 1, wherein a thickness of the intermediate stacked portion is between 5000 Å

and 10000 Å

.

20. The semiconductor device according to claim 1, wherein a thickness of the intermediate stacked portion is between 200 nm and 500 nm.

21. The semiconductor device according to claim 1, wherein a thickness of the metal layer is between 1 μ

m and 0.5 μ

m.

22. The semiconductor device according to claim 1, further comprising a gate withstand voltage holding region formed so as to be extended to a backside direction of the semiconductor substrate from the bottom surface of the gate trench.

23. The semiconductor device according to claim 22, wherein the gate withstand voltage holding region having a thickness of about 0.8 μ

m is formed from the bottom surface of the gate trench to the backside of the semiconductor substrate.

24. The semiconductor device according to claim 1, wherein the first source region has a substantially uniform thickness in a cross sectional view.

25. The semiconductor device according to claim 1, wherein the interlayer insulating film has a convex portion which is formed so as to be extended to the gate trench in a cross sectional view.

26. The semiconductor device according to claim 1, wherein a length of the bottom surface of the gate trench is longer than a length of the first body region in a cross sectional view.

27. The semiconductor device according to claim 1, wherein the semiconductor substrate is a SiC substrate.

28. The semiconductor device according to claim 1, wherein the first source region and the first body region are formed at a first side direction of the gate trench, and a diode region is formed at a second side direction of the gate trench, so that an asymmetrical portion formed so as to be asymmetrical with respect to the gate trench is included in the semiconductor device.

29. The semiconductor device according to claim 28, further comprising a body contact region formed at the surface of the semiconductor substrate so as to be electrically connected to the first body region, at the first side direction of the gate trench.

30. The semiconductor device according to claim 29, further comprising a second source region having a first conductivity type, formed at the second side direction of the gate trench in a cross sectional view.

31. The semiconductor device according to claim 30, wherein the first conductivity type is an n type and the second conductivity type is a p type.