Semiconductor structure including isolations and method for manufacturing the same

• US 10,515,845 B2
• Filed: 02/22/2018
• Issued: 12/24/2019
• Est. Priority Date: 11/09/2017
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Lo, Wen-Shun, Chang, Yu-Chi, Tsui, Felix Ying-Kit
• Primary Examiner(s): Prenty, Mark V
• Application Number:
  US15/902,422
• Publication Number:
  US 20190139816A1
• Time in Patent Office: 670 Days
• CPC Class Codes: H01L 21/26513 of electrically active species
• CPC Class Codes: H01L 21/266 using masks H01L21/26586 takes precedence
• CPC Class Codes: H01L 21/324 Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering H01L21/20 - H01L21/288 and H01L21/302 - H01L21/322 take precedence
• CPC Class Codes: H01L 21/76237 introducing impurities in trench side or bottom walls, e.g. for forming channel stoppers or alter isolation behavior
• CPC Class Codes: H01L 21/823481 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H10B 10/12 comprising a MOSFET load element
• CPC Class Codes: H10B 10/18 Peripheral circuit regions

Abstract

A method for manufacturing a semiconductor structure including isolations includes receiving a substrate including a first region and a second region; forming a patterned hard mask, the patterned hard mask including a first opening exposing a portion of the first region and a second opening exposing a portion of the second region; removing portions of the substrate to form a first trench in the first region and to form a second trench in the second region; performing an ion implantation to a portion of the patterned hard mask in the first region and a portion of the substrate exposed from the first trench; enlarging the first opening to form a third opening over the first trench and enlarging the second opening to form a fourth opening over the second trench; and forming a first isolation by filling the first trench and a second isolation by filling the second trench.

Claims

1. A method for manufacturing a semiconductor structure, comprising:

receiving a substrate;

forming a patterned hard mask over the substrate, the patterned hard mask comprising at least a first opening;

forming at least a trench in the substrate through the first opening of the patterned hard mask, and at least a portion of the substrate being exposed from the trench;

performing an ion implantation to the patterned hard mask and the portion of the substrate exposed from the trench to form a doped region in the substrate;

enlarging the first opening by removing a portion of the patterned hard mask to form a second opening over the trench; and

forming an isolation by filling the trench,

wherein the forming of the isolation filling the trench further comprises;

forming an insulating material to fill the trench, wherein a top surface of the isolation is lower than a top surface of the patterned hard mask; and

removing the patterned hard mask.

2. The method of claim 1, wherein the ion implantation comprises implanting Ge, N, or Ar.

3. The method of claim 1, further comprising performing a thermal operation before forming the insulating material to fill the trench.

19. The method of claim 1, further comprising forming a gate structure over the isolation and the substrate.

20. The method of claim 19, wherein a topmost surface of the isolation is between a topmost surface of the substrate and a bottom most surface of the gate structure.

4. A method for manufacturing a semiconductor structure, comprising:

receiving a substrate comprising a first region and a second region defined thereon;

forming a patterned hard mask over the substrate, the patterned hard mask comprising a first opening exposing a portion of the first region and a second opening exposing a portion of the second region;

removing portions of the substrate to form a first trench in the first region through the first opening and to form a second trench in the second region through the second opening, wherein a width of the first trench is greater than a width of the second trench;

performing an ion implantation to a portion of the patterned hard mask in the first region and a portion of the substrate exposed from the first trench in the first region;

enlarging the first opening to form a third opening over the first trench and enlarging the second opening to form a fourth opening over the second trench; and

forming a first isolation filling the first trench and a second isolation filling the second trench.

5. The method of claim 4, further comprising forming a protecting layer over the second region before performing the ion implantation, and removing the protecting layer before enlarging the first opening and enlarging the second opening.

6. The method of claim 4, wherein the ion implantation comprises implanting Ge, N, or Ar.

7. The method of claim 4, wherein the patterned hard mask in the first region comprises a first etching rate with respect to an etchant after the ion implantation, the patterned hard mask in the second region comprises a second etching rate with respect to the etchant after the ion implantation, and the first etching rate is greater than the second etching rate.

8. The method of claim 4, wherein the first opening and the third opening comprise a first width difference, the second opening and the fourth opening comprise a second width difference, and the first width difference is greater than the second width difference.

9. The method of claim 4, wherein the forming the first isolation in the first trench and the second isolation in the second trench further comprises:

performing a thermal operation;

forming an insulating material to fill the first trench and the second trench, and a top surface of the insulating material being lower than a top surface of the patterned hard mask; and

removing the patterned hard mask.

10. The method of claim 9, the ion implantation is performed to form a doped region in the first trench.

11. The method of claim 10, wherein the doped region is re-crystallized by the thermal operation.

12. The method of claim 4, wherein a top portion of the first isolation is different from a top portion of the second isolation.

13. A method for manufacturing a semiconductor structure, comprising:

receiving a substrate comprising a first region and a second region defined thereon;

forming a patterned hard mask over the substrate, the patterned hard mask comprising a first opening exposing a portion of the first region and a second opening exposing a portion of the second region;

forming a first trench in the first region through the first opening and a second trench in the second region through the second opening;

performing an ion implantation to a portion of the patterned hard mask in the first region and a portion of the substrate exposed from the first trench in the first region to form a doped region in the portion of the substrate exposed from the first trench;

enlarging the first opening to form a third opening over the first trench and enlarging the second opening to form a fourth opening over the second trench;

performing a thermal operation;

forming a first isolation filling the first trench and a second isolation filling the second trench;

removing the patterned hard mask; and

forming a first gate structure over the first isolation and a second gate structure over the second isolation.

14. The method of claim 13, wherein a width of the first trench is greater than a width of the second trench.

15. The method of claim 13, wherein the patterned hard mask in the first region comprises a first etching rate with respect to an etchant after the ion implantation, the patterned hard mask in the second region comprises a second etching rate with respect to the etchant after the ion implantation, and the first etching rate is greater than the second etching rate.

16. The method of claim 13, wherein the first opening and the third opening comprise a first width difference, the second opening and the fourth opening comprise a second width difference, and the first width difference is greater than the second width difference.

17. The method of claim 13, wherein the doped region is re-crystallized by the thermal operation.

18. The method of claim 13, wherein the first gate structure is in contact with the first isolation and a portion of the substrate, and the second gate structure is in contact with the second isolation and a portion of the substrate.