Semiconductor package structure having a multi-thermal interface material structure

• US 10,515,869 B1
• Filed: 05/29/2018
• Issued: 12/24/2019
• Est. Priority Date: 05/29/2018
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Yeh, Ting-Yu, Hsu, Chia-Hao, Chen, Weiming Chris, Ting, Kuo-Chiang, Yu, Tu-Hao, Hou, Shang-Yun
• Primary Examiner(s): Soward, Ida M
• Application Number:
  US15/992,045
• Publication Number:
  US 20190371700A1
• Time in Patent Office: 574 Days
• CPC Class Codes: H01L 21/563 Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
• CPC Class Codes: H01L 22/32 Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors arrangements for conducting electric current to or from the solid state body in operation H01L23/48
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/29011 comprising apertures or cavities
• CPC Class Codes: H01L 2224/29013 being rectangular or square
• CPC Class Codes: H01L 2224/2929 with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
• CPC Class Codes: H01L 2224/29309 Indium [In] as principal constituent
• CPC Class Codes: H01L 2224/29324 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/29339 Silver [Ag] as principal constituent
• CPC Class Codes: H01L 2224/29347 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/29386 with a principal constituent of the material being a non metallic, non metalloid inorganic material
• CPC Class Codes: H01L 2224/32245 the item being metallic
• CPC Class Codes: H01L 2224/3303 Layer connectors having different sizes, e.g. different heights or widths
• CPC Class Codes: H01L 2224/33151 being uniform, i.e. having a uniform pitch across the array
• CPC Class Codes: H01L 2224/3316 Random layout, i.e. layout with no symmetry
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/73253 Bump and layer connectors
• CPC Class Codes: H01L 23/3121 a substrate forming part of the encapsulation
• CPC Class Codes: H01L 23/3735 Laminates or multilayers, e.g. direct bond copper ceramic substrates
• CPC Class Codes: H01L 23/3737 : Organic materials with or without a thermoconductive filler
• CPC Class Codes: H01L 23/42 : Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
• CPC Class Codes: H01L 23/562 : Protection against mechanical damage H01L23/02, H01L23/28 take precedence
• CPC Class Codes: H01L 24/17 : of a plurality of bump connectors
• CPC Class Codes: H01L 24/29 : of an individual layer connector
• CPC Class Codes: H01L 24/32 : of an individual layer connector
• CPC Class Codes: H01L 24/33 : of a plurality of layer connectors
• CPC Class Codes: H01L 27/0688 : Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/013 : Alloys
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/0503 : 13th Group
• CPC Class Codes: H01L 2924/05032 : AlN
• CPC Class Codes: H01L 2924/05432 : Al2O3
• CPC Class Codes: H01L 2924/05442 : SiO2
• CPC Class Codes: H01L 2924/0665 : Epoxy resin
• CPC Class Codes: H01L 2924/3511 : Warping
• CPC Class Codes: H01L 2924/3512 : Cracking

Abstract

A semiconductor package structure includes a substrate, a first semiconductor and a second semiconductor over the substrate, and a multi-TIM structure disposed over the first semiconductor die and the second semiconductor die. The first semiconductor die includes a first heat output and the second semiconductor die includes a second heat output less than the first heat output. The multi-TIM structure includes a first TIM layer disposed over at least a portion of the first semiconductor die and a second TIM layer. A thermal conductivity of the first TIM layer is higher than a thermal conductivity of the second TIM layer. The first TIM layer covers the first semiconductor die.

Claims

1. A semiconductor package structure comprising:

a substrate;

a plurality of semiconductor dies over the substrate; and

a multi-thermal interface material (TIM) structure over the plurality of semiconductor dies,

wherein the multi-TIM structure comprises a first TIM layer and a second TIM layer, and a thermal conductivity (Tk) of the first TIM layer is different from a thermal conductivity of the second TIM layer, the first TIM layer overlaps a portion of each of the plurality of semiconductor dies, and the second TIM layer overlaps another portion of each of the plurality of semiconductor dies.

2. The semiconductor package structure of claim 1, wherein the first TIM layer is separated from the second TIM layer by an air gap.

3. The semiconductor package structure of claim 1, wherein the first TIM layer is in contact with the second TIM layer.

4. The semiconductor package structure of claim 1, wherein the second TIM layer surrounds the first TIM layer from a top view.

5. The semiconductor package structure of claim 1, wherein the plurality of semiconductor dies are arranged along a first direction, and the first TIM layer and the second TIM layer are arranged along a second direction different from the first direction.

6. The semiconductor package structure of claim 1, wherein the plurality of semiconductor dies, the first TIM layer and the second TIM layer are arranged along a same direction.

7. The semiconductor package structure of claim 1, wherein the multi-TIM structure further comprises a third TIM layer, and the first TIM layer is disposed between the second TIM layer and the third TIM layer from a top view.

8. The semiconductor package structure of claim 1, wherein the multi-TIM structure has a consistent thickness.

9. The semiconductor package structure of claim 1, wherein an area of the first TIM layer is greater than an area of the second TIM layer.

10. A semiconductor package structure comprising:

a substrate;

a first semiconductor die and a second semiconductor die disposed over the substrate, wherein the first semiconductor die includes a first heat output and the second semiconductor die includes a second heat output less than the first heat output; and

a multi-TIM structure disposed over the first semiconductor die and the second semiconductor die, the multi-TIM structure comprising a first TIM layer disposed over at least a portion of the first semiconductor die and a second TIM layer,

wherein a thermal conductivity of the first TIM layer is greater than a thermal conductivity of the second TIM layer.

11. The semiconductor package structure of claim 10, wherein the thermal conductivity of the first TIM layer is greater than approximately 10 watts per meter kelvin (W/mK).

12. The semiconductor package structure of claim 10, wherein the thermal conductivity of the second TIM layer is smaller than approximately 10 W/mK.

13. The semiconductor package structure of claim 10, wherein the first TIM layer comprises a base material and thermal conductive fillers, the base material comprises plastics, adhesives, glues, epoxies, polymers, thermoplastics, silicone, grease, oil or resin, and the thermal conductive fillers comprise aluminum oxide (AlO), boron nitride (BN), aluminum nitride (AlN), aluminum (Al), copper (Cu), silver (Ag), or indium (In).

14. The semiconductor package structure of claim 10, wherein the second TIM layer comprises polymer.

15. The semiconductor package structure of claim 10, wherein an adhesion of the first TIM layer is different from an adhesion of the second TIM layer.

16. The semiconductor package structure of claim 10, further comprising a heat sink disposed over the multi-TIM structure and in contact with the multi-TIM structure.

17. A semiconductor package structure comprising:

a substrate comprising a first region and a second region;

a plurality of semiconductor dies and in the first region of the substrate; and

a multi-TIM structure over the plurality of semiconductor dies in the first region, the multi-TIM structure comprising at least a first TIM layer and at least a second TIM layer,

wherein an adhesion of the first TIM layer is less than an adhesion of the second TIM layer, and the second TIM layer is disposed over corners of the first region.

18. The semiconductor package structure of claim 17, wherein a thermal conductivity of the first TIM layer is different from a thermal conductivity of the second TIM layer.

19. The semiconductor package structure of claim 17, wherein the second TIM layer further covers a periphery of the first region.

20. The semiconductor package structure of claim 17, wherein the second TIM layer surrounds the first TIM layer from a top view.