Chip package with fan-out structure
First Claim
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1. A chip package, comprising:
- a semiconductor die;
a protection layer surrounding the semiconductor die;
a dielectric layer over the semiconductor die and the protection layer, wherein the dielectric layer has an upper surface with cutting scratches, wherein bottoms of the cutting scratches are positioned at height levels that are lower than a topmost surface of the dielectric layer and higher than a topmost surface of the semiconductor die; and
a conductive layer over the dielectric layer and filling some of the cutting scratches.
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Abstract
A chip package is provided. The chip package includes a semiconductor die and a protection layer surrounding the semiconductor die. The chip package also includes a dielectric layer over the semiconductor die and the protection layer. The dielectric layer has an upper surface with cutting scratches. The chip package further includes a conductive layer over the dielectric layer and filling some of the cutting scratches.
24 Citations
20 Claims
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1. A chip package, comprising:
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a semiconductor die; a protection layer surrounding the semiconductor die; a dielectric layer over the semiconductor die and the protection layer, wherein the dielectric layer has an upper surface with cutting scratches, wherein bottoms of the cutting scratches are positioned at height levels that are lower than a topmost surface of the dielectric layer and higher than a topmost surface of the semiconductor die; and a conductive layer over the dielectric layer and filling some of the cutting scratches. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A chip package, comprising:
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a semiconductor die; a protection layer surrounding the semiconductor die; a dielectric layer over the semiconductor die and the protection layer; and a conductive layer over the dielectric layer, wherein the conductive layer has a plurality of protruding portions extending into the dielectric layer, and bottoms of the protruding portions are positioned at height levels that are lower than a topmost surface of the dielectric layer and higher than a topmost surface of the semiconductor die. - View Dependent Claims (12, 13, 14, 15)
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16. A chip package, comprising:
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a semiconductor die; a protection layer surrounding the semiconductor die; a dielectric layer over the semiconductor die and the protection layer; and a conductive layer over the dielectric layer, wherein an interface between the conductive layer and the dielectric layer has an undulate morphology, and bottoms of the interface with the undulated morphology are positioned at height levels that are lower than a topmost surface of the dielectric layer and higher than a topmost surface of the semiconductor die. - View Dependent Claims (17, 18, 19, 20)
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Specification