Method for forming semiconductor package structure with twinned copper layer

• US 10,515,923 B2
• Filed: 05/31/2017
• Issued: 12/24/2019
• Est. Priority Date: 05/31/2017
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Chang, Jung-Hua, Lin, Jing-Cheng, Tsai, Po-Hao
• Primary Examiner(s): Parker, Allen L
• Assistant Examiner(s): Ramallo, Gustavo G
• Application Number:
  US15/609,523
• Publication Number:
  US 20180350765A1
• Time in Patent Office: 937 Days
• CPC Class Codes: H01L 21/02603 Nanowires
• CPC Class Codes: H01L 21/4846 Leads on or in insulating or insulated substrates, e.g. metallisation H01L21/4821 takes precedence; metallisation of ceramics in general C04B41/51; printed circuits H05K3/00
• CPC Class Codes: H01L 21/4853 Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
• CPC Class Codes: H01L 21/486 Via connections through the substrate with or without pins
• CPC Class Codes: H01L 21/563 Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
• CPC Class Codes: H01L 21/568 Temporary substrate used as encapsulation process aid H01L21/4832 and H01L21/566 take precedence
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 21/6836 Wafer tapes, e.g. grinding or dicing support tapes adhesive tapes in general C09J7/20
• CPC Class Codes: H01L 2221/68331 of passive members, e.g. die mounting substrate
• CPC Class Codes: H01L 2221/68345 used as a support during the manufacture of self supporting substrates
• CPC Class Codes: H01L 2221/68359 used as a support during manufacture of interconnect decals or build up layers
• CPC Class Codes: H01L 2221/68372 used to support a device or wafer when forming electrical connections thereto when forming bonding pads H01L24/03; when forming bump connectors H01L24/11; when forming layer connectors H01L24/27
• CPC Class Codes: H01L 2224/18 High density interconnect [HDI] connectors; Manufacturing methods related thereto
• CPC Class Codes: H01L 2224/215 Material
• CPC Class Codes: H01L 2224/27462 Electroplating
• CPC Class Codes: H01L 2224/2919 with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
• CPC Class Codes: H01L 2224/3003 Layer connectors having different sizes, e.g. different heights or widths
• CPC Class Codes: H01L 2224/3012 Layout
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73265 : Layer and wire connectors
• CPC Class Codes: H01L 2224/821 : Forming a build-up interconnect
• CPC Class Codes: H01L 2225/1035 : the device being entirely enclosed by the support, e.g. high-density interconnect [HDI]
• CPC Class Codes: H01L 2225/1058 : Bump or bump-like electrical connections, e.g. balls, pillars, posts
• CPC Class Codes: H01L 23/3107 : the device being completely enclosed
• CPC Class Codes: H01L 23/3128 : the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/49816 : Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/49822 : Multilayer substrates multilayer metallisation on monolayer substrate H01L23/498
• CPC Class Codes: H01L 23/49866 : characterised by the materials materials of the substrates H01L23/14, of the lead-frames H01L23/49579
• CPC Class Codes: H01L 23/5389 : the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 24/02 : Bonding areas on insulating substrates, e.g. chip carriers, H01L23/49816, H01L23/49838, H01L23/5389; Manufacturing methods related thereto
• CPC Class Codes: H01L 24/19 : Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 24/20 : Structure, shape, material or disposition of high density interconnect preforms
• CPC Class Codes: H01L 24/24 : of an individual high density interconnect connector
• CPC Class Codes: H01L 24/25 : of a plurality of high density interconnect connectors
• CPC Class Codes: H01L 24/27 : Manufacturing methods
• CPC Class Codes: H01L 24/30 : of a plurality of layer connectors
• CPC Class Codes: H01L 25/105 : the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0001 : Technical content checked by a classifier
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: Y10S 977/762 : Nanowire or quantum wire, i.e. axially elongated structure having two dimensions of 100 nm or less

Abstract

A semiconductor package structure is provided. The semiconductor package structure includes a chip structure. The semiconductor package structure includes a first conductive structure over the chip structure. The first conductive structure is electrically connected to the chip structure. The first conductive structure includes a first transition layer over the chip structure, and a first conductive layer on the first transition layer. The first conductive layer is substantially made of twinned copper.

Claims

1. A method for forming a semiconductor package structure, comprising:

performing a pulse electroplating process over a chip structure to form a transition layer over the chip structure, wherein the transition layer comprises twinned copper;

performing a direct current electroplating process on the transition layer to form a first conductive layer over the transition layer, wherein the first conductive layer is substantially made of twinned copper; and

after the formation of the first conductive layer, forming a second conductive layer over the first conductive layer, wherein a first average roughness of a first top surface of the second conductive layer is less than a second average roughness of a second top surface of the first conductive layer.

2. The method for forming a semiconductor package structure as claimed in claim 1, wherein the chip structure comprises a conductive feature, and the method further comprises:

before the formation of the transition layer, forming a dielectric layer over the chip structure, wherein the dielectric layer has an opening exposing the conductive feature of the chip structure;

forming a seed layer over the dielectric layer and the conductive feature;

forming a mask layer over the seed layer, wherein the mask layer has a trench exposing a portion of the seed layer over the conductive feature, and the transition layer is formed over the portion of the seed layer; and

after the formation of the first conductive layer, removing the mask layer and the seed layer under the mask layer.

3. The method for forming a semiconductor package structure as claimed in claim 1, wherein the formation of the transition layer and the formation of the first conductive layer use a same electroplating solution and are performed in a same plating tank.

4. The method for forming a semiconductor package structure as claimed in claim 1, wherein the formation of the transition layer and the formation of the first conductive layer use a first electroplating solution, the formation of the second conductive layer use a second electroplating solution, and the first electroplating solution is different from the second electroplating solution.

5. The method for forming a semiconductor package structure as claimed in claim 1, further comprising:

providing a molding layer surrounding the chip structure before performing the pulse electroplating process over the chip structure, wherein the transition layer is further formed over the molding layer.

6. The method for forming a semiconductor package structure as claimed in claim 5, wherein a twinned copper volume percentage in the transition layer increases in a direction away from the chip structure and the molding layer.

7. The method for forming a semiconductor package structure as claimed in claim 1, wherein the transition layer and the first conductive layer together form a conductive line.

8. The method for forming a semiconductor package structure as claimed in claim 1, wherein the twinned copper in the first conductive layer comprises (111)-oriented twinned copper.

9. The method for forming a semiconductor package structure as claimed in claim 1, further comprising:

forming a dielectric layer over the chip structure before performing the pulse electroplating process over the chip structure, wherein the transition layer and the first conductive layer are formed over the dielectric layer and extend through the dielectric layer to be electrically connected to the chip structure, and the dielectric layer is in direct contact with the chip structure.

10. A method for forming a semiconductor package structure, comprising:

providing a chip structure and a molding layer surrounding the chip structure;

performing a first pulse electroplating process over the chip structure and the molding layer to form a first transition layer over the chip structure and the molding layer, wherein the first transition layer comprises twinned copper;

performing a first direct current electroplating process on the first transition layer to form a first conductive layer over the first transition layer, wherein the first conductive layer is substantially made of twinned copper, the first conductive layer is thicker than the first transition layer, and the first transition layer and the first conductive layer together form a first conductive line; and

forming a second conductive layer over the first conductive layer, wherein an average volume percentage of the twinned copper in the first conductive layer is greater than an average volume percentage of the twinned copper in the second conductive layer.

11. The method for forming a semiconductor package structure as claimed in claim 10, further comprising:

forming a seed layer over the chip structure and the molding layer before performing the first pulse electroplating process over the chip structure and the molding layer, wherein the first transition layer is formed over the seed layer, and the seed layer is in direct contact with the chip structure and the first transition layer.

12. The method for forming a semiconductor package structure as claimed in claim 10, further comprising:

forming a second conductive line over the first conductive line after the first conductive line is formed, wherein a first average line width of the first conductive line is less than a second average line width of the second conductive line, and the second conductive line is in direct contact with the first conductive line.

13. The method for forming a semiconductor package structure as claimed in claim 12, wherein the formation of the second conductive line over the first conductive line comprises:

performing a second pulse electroplating process over the first conductive line to form a second transition layer over the first conductive line, wherein the second transition layer comprises twinned copper; and

performing a second direct current electroplating process on the second transition layer to form a third conductive layer over the second transition layer, wherein the third conductive layer is substantially made of twinned copper, the third conductive layer is thicker than the second transition layer, and the second transition layer and the third conductive layer together form the second conductive line.

14. The method for forming a semiconductor package structure as claimed in claim 10, wherein the formation of the first transition layer and the formation of the first conductive layer use a same electroplating solution and are performed in a same plating tank.

15. The method for forming a semiconductor package structure as claimed in claim 10, wherein a twinned copper volume percentage in the transition layer increases in a direction away from the chip structure and the molding layer.

16. A method for forming a semiconductor package structure, comprising:

providing a chip structure, a conductive via structure, and a molding layer surrounding the chip structure and the conductive via structure;

performing a pulse electroplating process over the conductive via structure and the molding layer to form a first transition layer over the conductive via structure and the molding layer, wherein the first transition layer comprises twinned copper; and

performing a direct current electroplating process on the first transition layer to form a first conductive layer over the first transition layer, wherein the first conductive layer is substantially made of twinned copper, and the first transition layer and the first conductive layer together form a first conductive line, and an average volume percentage of the twinned copper in the first conductive layer is greater than an average volume percentage of the twinned copper in the first transition layer.

17. The method for forming a semiconductor package structure as claimed in claim 16, further comprising:

forming a seed layer over the conductive via structure and the molding layer before performing the pulse electroplating process over the conductive via structure and the molding layer, wherein the first transition layer is formed over the seed layer, and the seed layer is in direct contact with the conductive via structure and the first transition layer.

18. The method for forming a semiconductor package structure as claimed in claim 16, wherein the conductive via structure comprises a second transition layer and a second conductive layer, the second conductive layer is between the second transition layer and the first conductive line, the second transition layer comprises twinned copper, and a twinned copper volume percentage in the second transition layer increases toward the second conductive layer.

19. The method for forming a semiconductor package structure as claimed in claim 18, wherein the second conductive layer comprises twinned copper.

20. The method for forming a semiconductor package structure as claimed in claim 16, further comprising:

forming a dielectric layer over the chip structure, the conductive via structure, and the molding layer before performing the pulse electroplating process over the conductive via structure and the molding layer, wherein the first transition layer and the first conductive layer are formed over the dielectric layer and extend through the dielectric layer to be electrically connected to the conductive via structure, and the dielectric layer is in direct contact with the chip structure.