Three-layer package-on-package structure and method forming same

• US 10,515,930 B2
• Filed: 04/02/2018
• Issued: 12/24/2019
• Est. Priority Date: 04/29/2016
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Hung, Jui-Pin, Hsu, Feng-Cheng, Jeng, Shin-Puu
• Primary Examiner(s): Menz, Laura M
• Application Number:
  US15/942,807
• Publication Number:
  US 20180226378A1
• Time in Patent Office: 631 Days
• CPC Class Codes: H01L 21/31053 involving a dielectric removal step
• CPC Class Codes: H01L 21/4857 Multilayer substrates multilayer metallisation on monolayer substrate H01L21/4846
• CPC Class Codes: H01L 21/486 Via connections through the substrate with or without pins
• CPC Class Codes: H01L 21/56 Encapsulations, e.g. encapsulation layers, coatings
• CPC Class Codes: H01L 21/561 Batch processing
• CPC Class Codes: H01L 21/568 Temporary substrate used as encapsulation process aid H01L21/4832 and H01L21/566 take precedence
• CPC Class Codes: H01L 21/76885 By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
• CPC Class Codes: H01L 2224/02311 Additive methods
• CPC Class Codes: H01L 2224/0237 Disposition of the redistribution layers
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/12105 Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/2919 with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48106 the connector being orthogonal to a side surface of the semiconductor or solid-state body, e.g. parallel layout
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/73267 : Layer and HDI connectors
• CPC Class Codes: H01L 2224/81 : using a bump connector
• CPC Class Codes: H01L 2224/81005 : being a temporary or sacrificial substrate
• CPC Class Codes: H01L 2224/81815 : Reflow soldering
• CPC Class Codes: H01L 2224/83 : using a layer connector
• CPC Class Codes: H01L 2224/92244 : the second connecting process involving a build-up interconnect
• CPC Class Codes: H01L 2224/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2225/06506 : Wire or wire-like electrical connections between devices
• CPC Class Codes: H01L 2225/0651 : Wire or wire-like electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06513 : Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/0652 : Bump or bump-like direct electrical connections from substrate to substrate
• CPC Class Codes: H01L 2225/06548 : Conductive via connections through the substrate, container, or encapsulation
• CPC Class Codes: H01L 2225/06568 : the devices decreasing in size, e.g. pyramidical stack
• CPC Class Codes: H01L 2225/06572 : Auxiliary carrier between devices, the carrier having an electrical connection structure
• CPC Class Codes: H01L 2225/1023 : the support being an insulating substrate
• CPC Class Codes: H01L 2225/1035 : the device being entirely enclosed by the support, e.g. high-density interconnect [HDI]
• CPC Class Codes: H01L 2225/1058 : Bump or bump-like electrical connections, e.g. balls, pillars, posts
• CPC Class Codes: H01L 23/3128 : the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/481 : Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/49811 : Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads H01L23/49827 takes precedence
• CPC Class Codes: H01L 23/5383 : Multilayer substrates H01L23/5385 takes precedence; multilayer metallisation on monolayer substrates H01L23/538
• CPC Class Codes: H01L 23/5384 : Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors H01L23/5383, H01L23/5385 take precedence; pins attached to insulating substrates H01L23/49811
• CPC Class Codes: H01L 23/5389 : the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/19 : Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 24/20 : Structure, shape, material or disposition of high density interconnect preforms
• CPC Class Codes: H01L 24/29 : of an individual layer connector
• CPC Class Codes: H01L 24/32 : of an individual layer connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 24/81 : using a bump connector
• CPC Class Codes: H01L 24/83 : using a layer connector
• CPC Class Codes: H01L 24/92 : Specific sequence of method steps
• CPC Class Codes: H01L 24/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/0652 : the devices being arranged next and on each other, i.e. mixed assemblies
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/105 : the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/1431 : Logic devices
• CPC Class Codes: H01L 2924/1432 : Central processing unit [CPU]
• CPC Class Codes: H01L 2924/1436 : Dynamic random-access memory [DRAM]
• CPC Class Codes: H01L 2924/1438 : Flash memory
• CPC Class Codes: H01L 2924/15192 : Resurf arrangement of the internal vias
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19042 : being an inductor
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H01L 2924/19105 : in a side-by-side arrangement on a common die mounting substrate
• CPC Class Codes: H01L 2924/3511 : Warping
• CPC Class Codes: H01L 2924/37001 : Yield

Abstract

A method includes forming a first plurality of redistribution lines, forming a first metal post over and electrically connected to the first plurality of redistribution lines, and bonding a first device die to the first plurality of redistribution lines. The first metal post and the first device die are encapsulated in a first encapsulating material. The first encapsulating material is then planarized. The method further includes forming a second metal post over and electrically connected to the first metal post, attaching a second device die to the first encapsulating material through an adhesive film, encapsulating the second metal post and the second device die in a second encapsulating material, planarizing the second encapsulating material, and forming a second plurality of redistributions over and electrically coupling to the second metal post and the second device die.

Claims

1. A package comprising:

a first plurality of redistribution lines;

a first encapsulating material underlying the first plurality of redistribution lines;

a first metal post penetrating through the first encapsulating material, wherein the first metal post is electrically coupled to the first plurality of redistribution lines;

a first device die encapsulated in the first encapsulating material, wherein the first device die is bonded to the first plurality of redistribution lines through flip-chip bonding;

a second device die underlying and attached to the first encapsulating material through an adhesive film;

a second encapsulating material encapsulating the second device die therein;

a second metal post penetrating through the second encapsulating material and electrically connecting to the first metal post; and

a second plurality of redistribution lines underlying and electrically coupling to the second device die and the second metal post.

2. The package of claim 1, wherein the first device die and the second device die are laid out back-to-back.

3. The package of claim 1, wherein the second encapsulating material is in physical contact with the first encapsulating material.

4. The package of claim 1, wherein the first encapsulating material and the second encapsulating material have a distinguishable interface therebetween.

5. The package of claim 1, wherein the first encapsulating material comprises a base material and filler particles mixed in the base material, and the filler particles comprise partial particles having planar surfaces contacting the second encapsulating material.

6. The package of claim 1, wherein a lateral size of the second metal post is smaller than a lateral size of the first metal post, and the second metal post contacts a portion of a bottom surface of the first metal post.

7. The package of claim 1, wherein the first metal post extends laterally beyond edges of the second metal post.

8. The package of claim 1 further comprising a package comprising a third device die therein, wherein the package is bonded to the first plurality of redistribution lines through solder bonding.

9. The package of claim 1, wherein the first device die overlaps a portion of the first encapsulating material.

10. The package of claim 1, wherein the first metal post is in physical contact with the second metal post and a top surface of the second encapsulating material.

11. The package of claim 1 further comprising a passive device underlying and bonded to the first plurality of redistribution lines.

12. The package of claim 11, wherein the passive device is encapsulated in the first encapsulating material.

13. A package comprising:

a first plurality of redistribution lines;

a first encapsulating material underlying the first plurality of redistribution lines;

a first metal post penetrating through the first encapsulating material, wherein the first metal post is electrically coupled to the first plurality of redistribution lines;

a first device die encapsulated in the first encapsulating material, wherein the first device die is bonded to the first plurality of redistribution lines through flip-chip bonding, wherein a back surface of the first device die contacts the first encapsulating material to form a horizontal interface;

a second device die underlying and attached to the first encapsulating material through an adhesive film, wherein the first device die and the second device die are laid out back-to-back;

a second encapsulating material encapsulating the second device die therein;

a second metal post penetrating through the second encapsulating material and electrically connecting to the first metal post; and

a second plurality of redistribution lines underlying and electrically coupling to the second device die and the second metal post.

14. The package of claim 13, wherein the second encapsulating material is in physical contact with the first encapsulating material.

15. The package of claim 14, wherein the first encapsulating material and the second encapsulating material have a distinguishable interface therebetween.

16. The package of claim 13, wherein there is no die-attach film attached to the first device die.

17. A package comprising:

a first plurality of redistribution lines;

a first encapsulating material underlying the first plurality of redistribution lines;

a first metal post penetrating through the first encapsulating material, wherein the first metal post is electrically coupled to the first plurality of redistribution lines;

a first device die encapsulated in the first encapsulating material, wherein the first device die is bonded to the first plurality of redistribution lines through flip-chip bonding;

a second device die underlying and attached to the first encapsulating material through an adhesive film;

a second encapsulating material encapsulating the second device die therein;

a second metal post penetrating through the second encapsulating material, wherein the first metal post and the second metal post are in physical contact with each other; and

a second plurality of redistribution lines underlying and electrically coupling to the second device die and the second metal post.

18. The package of claim 17, wherein the first encapsulating material comprises a base material and filler particles mixed in the base material, and the filler particles comprise partial particles having planar surfaces contacting the second encapsulating material.

19. The package of claim 17, wherein a lateral size of the second metal post is smaller than a lateral size of the first metal post.

20. The package of claim 17, wherein the first device die overlaps a portion of the first encapsulating material.