3D semiconductor device and structure

• US 10,515,935 B2
• Filed: 05/12/2019
• Issued: 12/24/2019
• Est. Priority Date: 12/22/2012
• Status: Expired due to Fees

• Current Assignee: Monolithic 3D, Inc.
• Original Assignee: Monolithic 3D, Inc.
• Inventors: Or-Bach, Zvi, Cronquist, Brian
• Primary Examiner(s): Harriston, William A
• Application Number:
  US16/409,840
• Publication Number:
  US 20190273069A1
• Time in Patent Office: 226 Days
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: H01L 21/743 Making of internal connections, substrate contacts
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 2224/24146 the HDI interconnect connecting to the same level of the lower semiconductor or solid-state body at which the upper semiconductor or solid-state body is mounted
• CPC Class Codes: H01L 2225/06544 Design considerations for via connections, e.g. geometry or layout
• CPC Class Codes: H01L 2225/06589 Thermal management, e.g. cooling
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/485 consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts H01L23/4821, H01L23/4822, H01L23/4824, H01L23/4825 take precedence; materials H01L23/532, bond pads H01L24/02, bump connectors H01L24/10
• CPC Class Codes: H01L 23/522 including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
• CPC Class Codes: H01L 24/25 of a plurality of high density interconnect connectors
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 29/0673 oriented parallel to a substrate
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/66439 : with a one- or zero-dimensional channel, e.g. quantum wire FET, in-plane gate transistor [IPG], single electron transistor [SET], striped channel transistor, Coulomb blockade transistor with an active layer made of a group 13/15 material H01L29/66469
• CPC Class Codes: H01L 29/66621 : using etching to form a recess at the gate location etching of semiconductor bodies H01L21/302
• CPC Class Codes: H01L 29/775 : with one dimensional charge carrier gas channel, e.g. quantum wire FET
• CPC Class Codes: H01L 29/78 : with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H01L 29/785 : having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/78696 : characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621
• CPC Class Codes: H01L 2924/0002 : Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/01104 : Refractory metals
• CPC Class Codes: H01L 2924/12032 : Schottky diode
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/2064 : larger or equal to 1 micron less than 100 microns
• CPC Class Codes: H01L 2924/351 : Thermal stress
• CPC Class Codes: H10B 43/20 : characterised by three-dimensional arrangements, e.g. with cells on different height levels

Abstract

A 3D semiconductor device, the device including: a first single crystal layer; at least one first metal layer above the first single crystal layer; a second metal layer above the first metal layer; a plurality of first transistors atop the second metal layer; a plurality of second transistors atop the second transistors; a plurality of third transistors atop the second transistors; a third metal layer above the plurality of third transistors: a fourth metal layer above the third metal layer; and a second single crystal layer above the fourth metal layer; and a plurality of connecting metal paths from the fourth metal layer to the second metal layer, where at least one of the plurality of third transistors is aligned to at least one of the plurality of first transistors with less than 40 nm alignment error, where the fourth metal layer is providing global power distribution to the device.

Claims

1. A 3D semiconductor device, the device comprising:

a first single crystal layer;

at least one first metal layer above said first single crystal layer;

a second metal layer above said first metal layer;

a plurality of first transistors atop said second metal layer;

a plurality of second transistors atop said second transistors;

a plurality of third transistors atop said second transistors;

a third metal layer above said plurality of third transistors;

a fourth metal layer above said third metal layer; and

a second single crystal layer above said fourth metal layer; and

a plurality of connecting metal paths from said fourth metal layer to said second metal layer,

wherein at least one of said plurality of third transistors is aligned to at least one of said plurality of first transistors with less than 40 nm alignment error,

wherein said fourth metal layer is providing global power distribution to said device and said fourth metal layer is at least twice as thick as said third metal layer,

wherein said second metal layer provides local power distribution to said device and said second metal layer is substantially thicker than said first metal layer and said third metal layer,

wherein at least one of said connecting metal paths comprises a through layer via,

wherein said through layer via comprises a material and a majority of said material comprises tungsten,

wherein at least one of said plurality of second transistors comprises a first source, a first channel and a first drain,

wherein said first source, said first channel and said first drain have the same dopant type,

wherein said device comprises an array of memory cells, and

wherein at least one of said memory cells comprises one of said third transistors.

2. The 3D semiconductor device according to claim 1,

wherein at least one of said plurality of second transistors is self-aligned to at least one of said plurality of third transistors, being processed following the same lithography step.

3. The 3D semiconductor device according to claim 1,

wherein at least one of said plurality of second transistors comprises polysilicon.

4. The 3D semiconductor device according to claim 1,

wherein said second single crystal layer comprises a plurality of fourth transistors, and

wherein said device comprises memory periphery circuits comprising said fourth transistors.

5. The 3D semiconductor device according to claim 1,

wherein said second single crystal layer comprises a plurality of fourth transistors, and

wherein said device comprises Input/Output circuits comprising said fourth transistors.

6. The 3D semiconductor device according to claim 1,

wherein at least one of said plurality of second transistors comprises a gate all around structure, and

wherein formation of said gate all around structure comprises Atomic Layer Deposition (ALD).

7. The 3D semiconductor device according to claim 1,

wherein said second single crystal layer comprises a plurality of through layer vias.

8. A 3D semiconductor device, the device comprising:

a first single crystal layer comprising a plurality of first transistors;

at least one first metal layer interconnecting said plurality of first transistors,

wherein said interconnecting comprises forming a plurality of logic gates;

a second metal layer above said first metal layer;

a plurality of second transistors atop said second metal layer;

a third metal layer above said plurality of second transistors;

a plurality of third transistors atop said second transistors;

a fourth metal layer above said third metal layer; and

a plurality of connecting metal paths from said fourth metal layer to said second metal layer,

wherein at least one of said plurality of third transistors is aligned to at least one of said plurality of first transistors with less than 40 nm alignment error,

wherein said fourth metal layer is providing global power distribution to said device and said fourth metal layer is at least twice as thick as said third metal layer,

wherein said second metal layer provides local power distribution to said device and is substantially thicker than said first metal layer and said third metal layer,

wherein at least one of said connecting metal paths comprises a through layer via,

wherein said through layer via comprises a material and a majority of said material comprises tungsten,

wherein at least one of said second transistors comprises a first source, a first channel and a first drain,

wherein said first source, said first channel and said first drain have the same dopant type,

wherein said device comprises an array of memory cells, and

wherein at least one of said memory cells comprises one of said third transistors.

9. The 3D semiconductor device according to claim 8,

wherein said array of memory cells comprises NAND type memory.

10. The 3D semiconductor device according to claim 8,

wherein at least one of said plurality of second transistors is self-aligned to at least one of said plurality of third transistors, being processed following the same lithography step.

11. The 3D semiconductor device according to claim 8,

wherein at least one of said plurality of second transistors comprises polysilicon.

12. The 3D semiconductor device according to claim 8,

wherein fabrication processing of said device comprises first processing said first transistors followed by processing said second transistors and said third transistors above said first transistors, and

wherein said processing said first transistors accounts for the temperature associated with said processing said second transistors and said processing said third transistors by adjusting a process thermal budget of said first transistors accordingly.

13. The 3D semiconductor device according to claim 8,

wherein said plurality of logic gates comprise memory periphery circuits, and said memory periphery circuits comprise control of said array of memory cells.

14. The 3D semiconductor device according to claim 8, further comprising:

a second single crystal layer above said fourth metal layer.

15. A 3D semiconductor device, the device comprising:

a first single crystal layer comprising a plurality of first transistors;

at least one first metal layer interconnecting said plurality of first transistors,

wherein said interconnecting comprises forming a plurality of logic gates;

a second metal layer above said first metal layer;

a plurality of second transistors atop said second metal layer;

a third metal layer above said plurality of second transistors;

a plurality of third transistors atop said second transistors;

a fourth metal layer above said third metal layer; and

a plurality of connecting metal paths from said fourth metal layer to said second metal layer,

wherein at least one of said plurality of third transistors is aligned to at least one of said plurality of first transistors with less than 40 nm alignment error,

wherein said fourth metal layer is providing global power distribution to said device and said fourth metal layer is at least twice as thick as said third metal layer,

wherein said second metal layer provides local power distribution to said device and is substantially thicker than said first metal layer and said third metal layer,

wherein at least one of said connecting metal paths comprises a through layer via, and

wherein said through layer via comprises a material and a majority of said material comprises tungsten.

16. The 3D semiconductor device according to claim 15

wherein at least one of said plurality of third transistors comprises polysilicon.

17. The 3D semiconductor device according to claim 15,

wherein at least one of said plurality of third transistors comprises a source, a channel and a drain, and

wherein said source, said channel and said drain have the same dopant type.

18. The 3D semiconductor device according to claim 15,

wherein said device comprises more than one NAND type memory cell, and

wherein said NAND type memory cell comprises at least one of said plurality of second transistors.

19. The 3D semiconductor device according to claim 15,

wherein at least one of said plurality of second transistors is self-aligned to at least one of said plurality of third transistors, being processed following the same lithography step.

20. The 3D semiconductor device according to claim 15, further comprising:

a connecting via through said first single crystal layer.