Semiconductor device having fin structures of varying dimensions

• US 10,515,954 B2
• Filed: 03/18/2018
• Issued: 12/24/2019
• Est. Priority Date: 03/18/2018
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Liaw, Jhon-Jhy
• Primary Examiner(s): Soward, Ida M
• Application Number:
  US15/924,262
• Publication Number:
  US 20190287967A1
• Time in Patent Office: 646 Days
• CPC Class Codes: H01L 21/823431 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 27/0886 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/0924 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/1211 combined with field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/0692 Surface layout
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain
• CPC Class Codes: H01L 29/7855 with at least two independent gates
• CPC Class Codes: H01L 29/7856 with an non-uniform gate, e.g. varying doping structure, shape or composition on different sides of the fin, or different gate insulator thickness or composition on opposing fin sides H01L29/7855 takes precedence
• CPC Class Codes: H10B 10/125 the MOSFET being a thin film transistor [TFT]
• CPC Class Codes: H10B 12/056 the transistor being a FinFET
• CPC Class Codes: H10B 12/36 the transistor being a FinFET

Abstract

A semiconductor device includes at least one first fin, a first gate, a first gate dielectric layer, at least one second fin, a second gate electrode, and a second gate dielectric layer. The first fin has a first width. The first gate electrode crosses the first fin. The first gate dielectric layer is between the first fin and the first gate electrode and has a first thickness. The second fin has a second width greater than the first width. The second gate electrode crosses the second fin. The second gate dielectric layer is between the second fin and the second gate electrode and has a second thickness less than the first thickness.

Claims

1. A semiconductor device, comprising:

at least one first fin having a first width;

a first gate electrode crossing the first fin;

a first gate dielectric layer between the first fin and the first gate electrode and having a first thickness;

at least one second fin having a second width greater than the first width;

a second gate electrode crossing the second fin; and

a second gate dielectric layer between the second fin and the second gate electrode and having a second thickness less than the first thickness.

2. The semiconductor device of claim 1, wherein a ratio of the second width to the first width is in a range from 1.05 to 1.3.

3. The semiconductor device of claim 1, wherein a ratio of the first thickness to the second thickness is in a range from 1.2 to 2.

4. The semiconductor device of claim 1, wherein the first gate electrode has a first gate length along a longitudinal direction of the first fin, the second gate electrode defines a second gate length along a longitudinal direction of the second fin, and a ratio of the first gate length to the second gate length is in a range from 2 to 20.

5. The semiconductor device of claim 1, wherein a pair of the first fins are spaced from each other by a first spacing, and a pair of the second fins are spaced from each other by a second spacing less than the first spacing.

6. The semiconductor device of claim 1, wherein the first gate electrode extends along a first direction, and a plurality of the first fins are arranged along the first direction by a first pitch, wherein the second gate electrode extends along the first direction, and a plurality of the second fins are arranged along the first direction by a second pitch equal to the first pitch.

7. The semiconductor device of claim 1, further comprising an n-well region, wherein a plurality of the first fins are within the n-well region.

8. The semiconductor device of claim 1, further comprising:

a third fin having a third width greater than the first width and less than the second width; and

a third gate electrode crossing the third fin.

9. The semiconductor device of claim 8, further comprising:

an n-well region, wherein the third fin and a plurality of the second fins are located within the n-well region.

10. The semiconductor device of claim 9, wherein the third fin and the second fins extend along a first direction, and the semiconductor device further comprises:

a dummy gate between the third fin and the second fins and extending along a second direction orthogonal to the first direction.

11. The semiconductor device of claim 8, further comprising:

a third gate dielectric layer between the third fin and the third gate electrode and having a third thickness less than the first thickness.

12. The semiconductor device of claim 8, further comprising:

a first contact area overlapping with the second fin and having a first length; and

a second contact area overlapping with the third fin and having a second length shorter than the first length.

13. A semiconductor device, comprising:

a first n-well region;

a second n-well region spaced apart from the first n-well region;

a plurality of first fins located within the first n-well region and arranged along a first direction by a first pitch, wherein at least one of the first fins has a first width;

a first gate electrode crossing the first fins and extending along a second direction orthogonal to the first direction;

a plurality of second fins located within the second n-well region and arranged along the first direction by a second pitch equal to the first pitch, wherein at least one of the second fins has a second width greater than the first width; and

a second gate electrode crossing the second fins and extending along the second direction.

14. The semiconductor device of claim 13, further comprising:

a first gate dielectric layer between the first fins and the first gate electrode and having a first thickness; and

a second gate dielectric layer between the second fins and the second gate electrode and having a second thickness less than the first thickness.

15. The semiconductor device of claim 14, wherein a ratio of the first thickness to the second thickness is in a range from 1.2 to 2.

16. The semiconductor device of claim 14, wherein a ratio of the second width to the first width is in a range from 1.05 to 1.3.

17. The semiconductor device of claim 13, wherein the first fins are of an I/O circuit and the second fins are of a core circuit.

18. A semiconductor device comprising:

an I/O circuit including a first transistor, wherein the first transistor includes

a plurality of first fins that have a first width, and

a first gate electrode over the plurality of the first fins; and

a core circuit including a second transistor, wherein the second transistor includes

a single second fin that has a second width greater than the first width, and

a second gate electrode over the single second fin.

19. The semiconductor device of claim 18, wherein the first transistor further includes a first gate dielectric layer over the plurality of the first fins and the second transistor further includes a second gate dielectric layer that is over the single second fin and that has a greater thickness than the first gate dielectric layer.

20. The semiconductor device of claim 18, wherein the core circuit further includes a third transistor and the third transistor includes a plurality of third fins that have a third width greater than the first and second widths and a third gate electrode over the plurality of the third fins.