Semiconductor device having fins

• US 10,515,957 B2
• Filed: 07/31/2018
• Issued: 12/24/2019
• Est. Priority Date: 04/28/2017
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Fan, Chia-Sheng, Young, Bao-Ru, Hsieh, Tung-Heng
• Primary Examiner(s): Nguyen, Khiem D
• Application Number:
  US16/050,553
• Publication Number:
  US 20180337178A1
• Time in Patent Office: 511 Days
• CPC Class Codes: H01L 21/0217 the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz H01L21/02126 and H01L21/0214 take precedence
• CPC Class Codes: H01L 21/0223 formation by oxidation, e.g. oxidation of the substrate
• CPC Class Codes: H01L 21/02255 formation by thermal treatment H01L21/02252 takes precedence; after treatment of an insulating film H01L21/3105 and subgroups
• CPC Class Codes: H01L 21/823431 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823437 with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 21/823481 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 21/823821 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823828 with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 21/823878 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 27/0886 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/0924 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66553 using inside spacers, permanent or not

Abstract

A semiconductor device and method includes: forming a first fin and a second fin on a substrate; forming a dummy gate material over the first fin and the second fin; forming a recess in the dummy gate material between the first fin and the second fin; forming a sacrificial oxide on sidewalls of the dummy gate material in the recess; filling an insulation material between the sacrificial oxide on the sidewalls of the dummy gate material in the recess; removing the dummy gate material and the sacrificial oxide; and forming a first replacement gate over the first fin and a second replacement gate over the second fin.

Claims

1. A device comprising:

a first fin extending from a major surface of a substrate;

a second fin extending from the major surface of the substrate, the second fin and the first fin having parallel longitudinal axes;

a first isolation material surrounding the first fin and the second fin;

a first gate stack over the first fin;

a second gate stack over the second fin;

gate spacers adjacent the first gate stack and the second gate stack; and

a second isolation material contacting the first isolation material, the second isolation material disposed between the first gate stack and the second gate stack, the second isolation material having a longitudinal axis being parallel to the longitudinal axes of the first fin and the second fin, the second isolation material being different from the first isolation material,

wherein the second isolation material has a first width proximate the gate spacers, and a second width distal the gate spacers, the first width being greater than the second width, the first width and the second width being measured along a latitudinal axis of the second isolation material, the latitudinal axis of the second isolation material being perpendicular to the longitudinal axis of the second isolation material, the latitudinal axis of the second isolation material and the longitudinal axis of the second isolation material being parallel to the major surface of the substrate.

2. The device of claim 1, wherein the second isolation material comprises silicon nitride.

3. The device of claim 1, wherein the first gate stack comprises:

a first gate dielectric over the first isolation material and contacting sidewalls of the second isolation material; and

a first gate electrode over the first gate dielectric.

4. The device of claim 3, wherein the first gate electrode is disposed between the first fin and the second isolation material.

5. The device of claim 3, wherein top surfaces of the first gate electrode, the first gate dielectric, and the second isolation material are planar.

6. The device of claim 1, wherein the second isolation material is further disposed between neighboring ones of the gate spacers.

7. The device of claim 1, wherein sidewalls of the second isolation material form an obtuse angle with a plane parallel to the major surface of the substrate.

8. The device of claim 1, wherein the second isolation material has a uniform height.

9. A device comprising:

a first transistor comprising a first source region, a first drain region, and a first gate, the first transistor being in a first fin;

a second transistor comprising a second source region, a second drain region, and a second gate, the second transistor being in a second fin;

a first isolation material surrounding a lower portion of the first fin and a lower portion of the second fin;

a second isolation material on the first isolation material, the second isolation material separating the first gate from the second gate, a sidewall of the second isolation material forming an obtuse angle with a plane parallel to a major surface of the first isolation material, the first fin, the second fin, and the second isolation material each having a parallel longitudinal axis; and

a first inter-layer dielectric (ILD) on the first isolation material, the first ILD surrounding the first source region, the second source region, the first drain region, and the second drain region,

wherein the second isolation material has a middle portion with a first width and edge portions with a second width, the first width being less than the second width, the first width and the second width being measured along a latitudinal axis of the second isolation material, the latitudinal axis of the second isolation material being perpendicular to the longitudinal axis of the second isolation material, the latitudinal axis of the second isolation material and the longitudinal axis of the second isolation material being parallel to the major surface of the first isolation material.

10. The device of claim 9, wherein the first gate comprises:

a first gate dielectric contacting the first fin, the major surface of the first isolation material, and the sidewall of the second isolation material; and

a first gate electrode over the first gate dielectric.

11. The device of claim 10, wherein top surfaces of the first gate electrode, the first gate dielectric, and the second isolation material are planar.

12. The device of claim 9, further comprising:

a second ILD on the first ILD and the second isolation material; and

a first contact extending through the second ILD to physically and electrically connect to the first gate; and

a second contact extending through the first ILD and the second ILD to physically and electrically connect to the first source region.

13. The device of claim 9, wherein the second isolation material is silicon nitride.

14. The device of claim 9, wherein the middle portion and the edge portions of the second isolation material have a same height.

15. A device comprising:

a first fin extending from a substrate;

a second fin extending from the substrate;

a first isolation material surrounding the first fin and the second fin;

a second isolation material contacting the first isolation material, the second isolation material being disposed between the first fin and the second fin;

a first gate dielectric extending along a first sidewall of the second isolation material, a major surface of the first isolation material, sidewalls of the first fin, and a top surface of the first fin;

a first gate electrode contacting the first gate dielectric;

a second gate dielectric extending along a second sidewall of the second isolation material, the major surface of the first isolation material, sidewalls of the second fin, and a top surface of the second fin;

a second gate electrode contacting the second gate dielectric; and

gate spacers extending along sides of the first gate electrode, the second gate electrode, and the second isolation material,

wherein the second isolation material has a middle portion with a first width and edge Portions with a second width, the first width being less than the second width, the first width and the second width each being measured along a direction extending from the first gate dielectric to the second gate dielectric, the edge portions being disposed adjacent the gate spacers, the middle portion being disposed between the edge portions.

16. The device of claim 15, wherein the second isolation material is disposed between the first gate electrode and the second gate electrode.

17. The device of claim 15, wherein the first and second sidewalls of the second isolation material form obtuse angles with a plane parallel to the major surface of the first isolation material.

18. The device of claim 15, wherein top surfaces of the second isolation material, the first gate dielectric, the first gate electrode, the second gate dielectric, and the second gate electrode are planar.

19. The device of claim 18, wherein top surfaces of the middle portion and the edge portions of the second isolation material are planar.

20. The device of claim 15, wherein the second isolation material is silicon nitride.