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Enhanced channel strain to reduce contact resistance in NMOS FET devices

  • US 10,515,966 B2
  • Filed: 08/20/2018
  • Issued: 12/24/2019
  • Est. Priority Date: 09/18/2015
  • Status: Active Grant
First Claim
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1. A semiconductor device, comprising:

  • one or more n-type Fin FET structures; and

    one or more p-type Fin FET structures,wherein the n-type Fin FET structure comprises;

    a first gate structure formed over a channel region of a first fin structure; and

    first source/drain regions formed on the first fin structure on opposing sides of the first gate structure; and

    wherein the first source/drain regions have a first region and a second region, the first region being located closer to a surface of the first source/drain regions,the first region has a first dopant and the second region has a second dopant, andthe first dopant in the first region has a first lateral variance and the second dopant in the second region has a second lateral variance, wherein the first lateral variance is greater than the second lateral variance.

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