Dual-port semiconductor memory and first in first out (FIFO) memory having electrically floating body transistor

• US 10,515,968 B2
• Filed: 08/20/2018
• Issued: 12/24/2019
• Est. Priority Date: 11/16/2010
• Status: Active Grant

• Current Assignee: Zeno Semiconductor, Inc.
• Original Assignee: Zeno Semiconductor, Inc.
• Inventors: Widjaja, Yuniarto
• Primary Examiner(s): Nguyen, Viet Q
• Application Number:
  US16/105,730
• Publication Number:
  US 20190006367A1
• Time in Patent Office: 491 Days
• Field of Search: 36518505
• CPC Class Codes: G11C 11/40 using transistors
• CPC Class Codes: G11C 11/403 with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
• CPC Class Codes: G11C 11/405 with three charge-transfer gates, e.g. MOS transistors, per cell
• CPC Class Codes: G11C 2211/4016 Memory devices with silicon-on-insulator cells
• CPC Class Codes: G11C 7/00 Arrangements for writing information into, or reading information out from, a digital store G11C5/00 takes precedence; auxiliary circuits for stores using semiconductor devices G11C11/4063, G11C11/413
• CPC Class Codes: G11C 8/10 Decoders
• CPC Class Codes: G11C 8/16 Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups
• CPC Class Codes: H01Q 1/2283 mounted in or on the surface of a semiconductor substrate as a chip-type antenna or integrated with other components into an IC package
• CPC Class Codes: H10B 12/10 DRAM devices comprising bipolar components
• CPC Class Codes: H10B 12/20 DRAM devices comprising floating-body transistors, e.g. floating-body cells

Abstract

Multi-port semiconductor memory cells including a common floating body region configured to be charged to a level indicative of a memory state of the memory cell. The multi-port semiconductor memory cells include a plurality of gates and conductive regions interfacing with said floating body region. Arrays of memory cells and method of operating said memory arrays are disclosed for making a memory device.

Claims

1. An integrated circuit comprising:

a semiconductor memory array comprising a plurality of multi-port semiconductor memory cells arranged in a matrix of rows and columns, wherein each said multi-port semiconductor memory cell comprises;

a plurality of gates;

a common body region of a first conductivity type configured to store a charge that is indicative of a memory state of said memory cell;

a plurality of conductive regions of a second conductivity type,

wherein adjacent ones of each of said plurality of gates are separated by a respective one of the plurality of conductive regions, and wherein the common body region extends continuously beneath at least one of the plurality of conductive regions;

at least one of said plurality of conductive regions electrically connected to a back bias terminal,

wherein applying a voltage to said back bias terminal results in at least two stable common body region charge levels;

wherein said back bias terminal is commonly connected to at least two of said multi-port semiconductor memory cells; and

a control circuit configured to apply a voltage to said back bias terminal.

2. The integrated circuit of claim 1, wherein each of the plurality of gates is configured to provide at least one of read access from and write access to the multi-port semiconductor memory cell independently of all other of the plurality of gates.

3. The integrated circuit of claim 1, wherein each said multi-port semiconductor memory cell includes a total number of ports, said plurality of conductive regions comprises a total number of conductive regions, and said plurality of gates comprises a total number of gates, wherein the total number of ports is equal to the total number of gates, and further wherein the total number of conductive regions is one more than the total number of gates.

4. The integrated circuit of claim 1, wherein the plurality of conductive regions is in electrical communication with the common body region, and further wherein each of the plurality of conductive regions is spaced apart from all others of the plurality of conductive regions.

5. The integrated circuit of claim 1, wherein at least a portion of the common body region separates each of the plurality of conductive regions from all others of the plurality of conductive regions.

6. The integrated circuit of claim 1, wherein the plurality of conductive regions and the common body region form a plurality of diodes.

7. The integrated circuit of claim 1, wherein the multi-port semiconductor memory cell includes a fin structure, and further wherein the fin structure includes the common body region.

8. The integrated circuit of claim 7, wherein the fin structure is an elongate fin structure that includes a longitudinal axis, and further wherein the plurality of gates is spaced apart along the longitudinal axis.

9. The integrated circuit of claim 7, wherein the fin structure further includes the plurality of conductive regions.

10. The integrated circuit of claim 1, wherein said voltage applied to said back bias terminal is a constant positive voltage bias.

11. The integrated circuit of claim 1, wherein said voltage applied to said back bias terminal is a periodic pulse of positive voltage.

12. An integrated circuit comprising:

a semiconductor memory array comprising a plurality of multi-port semiconductor memory cells arranged in a matrix of rows and columns, wherein each said multi-port semiconductor memory cell comprises;

a plurality of transistors, each of the plurality of transistors comprising;

a common body region configured to store a charge that is indicative of a memory state of said multi-port semiconductor memory cell; and

a plurality of gates,

wherein said common body region is shared among the plurality of transistors;

a layer beneath said common body region wherein said common body region is positioned between said plurality of gates and said layer;

a back bias terminal connected to said layer and configured to perform at least one of injecting a charge into and extracting the charge out of the common body region to maintain said memory state of the multi-port semiconductor memory cell resulting in at least two stable common body region charge levels,

wherein said back bias terminal is commonly connected to at least two of said multi-port semiconductor memory cells; and

a control circuit configured to apply a voltage to said back bias terminal.

13. The integrated circuit of claim 12, wherein each of the plurality of gates is configured to provide at least one of read access from and write access to the multi-port semiconductor memory cell independently of all other of the plurality of gates.

14. The integrated circuit of claim 12, wherein each said multi-port semiconductor memory cell includes a total number of ports and wherein said plurality of gates consists of a total number of gates, wherein the total number of ports is equal to the total number of gates.

15. The integrated circuit of claim 14, wherein each said multi-port semiconductor memory cell further comprises a total number of conductive regions, wherein said total number of conductive regions is one more than said total number of gates.

16. The integrated circuit of claim 12, wherein the multi-port semiconductor memory cell includes a fin structure, and further wherein the fin structure includes the common body region.

17. The integrated circuit of claim 16, wherein the fin structure is an elongate fin structure that includes a longitudinal axis, and further wherein the plurality of gates is spaced apart along the longitudinal axis.

18. The integrated circuit of claim 16, wherein the fin structure further includes a plurality of conductive regions.

19. The integrated circuit of claim 12, wherein said voltage applied to said back bias terminal is a constant positive voltage bias.

20. The integrated circuit of claim 12, wherein said voltage applied to said back bias terminal is a periodic pulse of positive voltage.