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Dual-port semiconductor memory and first in first out (FIFO) memory having electrically floating body transistor

  • US 10,515,968 B2
  • Filed: 08/20/2018
  • Issued: 12/24/2019
  • Est. Priority Date: 11/16/2010
  • Status: Active Grant
First Claim
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1. An integrated circuit comprising:

  • a semiconductor memory array comprising a plurality of multi-port semiconductor memory cells arranged in a matrix of rows and columns, wherein each said multi-port semiconductor memory cell comprises;

    a plurality of gates;

    a common body region of a first conductivity type configured to store a charge that is indicative of a memory state of said memory cell;

    a plurality of conductive regions of a second conductivity type,wherein adjacent ones of each of said plurality of gates are separated by a respective one of the plurality of conductive regions, and wherein the common body region extends continuously beneath at least one of the plurality of conductive regions;

    at least one of said plurality of conductive regions electrically connected to a back bias terminal,wherein applying a voltage to said back bias terminal results in at least two stable common body region charge levels;

    wherein said back bias terminal is commonly connected to at least two of said multi-port semiconductor memory cells; and

    a control circuit configured to apply a voltage to said back bias terminal.

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