Semiconductor device and manufacturing method thereof

• US 10,515,969 B2
• Filed: 11/17/2016
• Issued: 12/24/2019
• Est. Priority Date: 11/17/2016
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Hsu, Jordan, Lin, Yu-Kuan, Lu, Shau-Wei, Yang, Chang-Ta, Wang, Ping-Wei, Lo, Kuo-Hung
• Primary Examiner(s): Nguyen, Sophia T
• Application Number:
  US15/354,052
• Publication Number:
  US 20180138185A1
• Time in Patent Office: 1,132 Days
• CPC Class Codes: H01L 21/823412 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823431 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823821 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823878 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 21/823892 with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 27/0886 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/0922 Combination of complementary transistors having a different structure, e.g. stacked CMOS, high-voltage and low-voltage CMOS
• CPC Class Codes: H01L 27/0924 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/0928 comprising both N- and P- wells in the substrate, e.g. twin-tub
• CPC Class Codes: H01L 29/4958 with a multiple layer structure
• CPC Class Codes: H01L 29/4966 the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66803 with a step of doping the vertical sidewall, e.g. using tilted or multi-angled implants
• CPC Class Codes: H10B 10/12 comprising a MOSFET load element

Abstract

A semiconductor device includes a substrate, a first transistor, and a second transistor. The first transistor is disposed on the substrate. The second transistor is disposed on the substrate. A gate of the first transistor and a gate of the second transistor are integrally formed, and the first transistor and the second transistor have different threshold voltages.

Claims

1. A semiconductor device comprising:

a substrate having a write portion and a read portion, wherein the write portion includes a first well and a second well that is spaced from the first well and that has the same conductivity type as the first well;

a first transistor disposed on the first well of the write portion of the substrate;

a second transistor disposed on the read portion of the substrate, wherein a gate of the first transistor and a gate of the second transistor are integrally formed, and the first transistor and the second transistor have different threshold voltages;

third and fourth transistors disposed on the second well of the write portion of the substrate, wherein the first and third transistors have the same threshold voltage and the third and fourth transistors have the same channel doping concentration, wherein the fourth transistor comprises;

an active region; and

a gate disposed on the active region of the fourth transistor and separated from the gates of the first and second transistors; and

a fifth transistor disposed on the first well of the write region of the substrate, wherein the fifth transistor has a channel doping concentration lower than a channel doping concentration of the first transistor.

2. The semiconductor device of claim 1, wherein the gates of the first transistor and the second transistor are metal gates.

3. The semiconductor device of claim 1, wherein the first transistor is a transistor of a write port of a static random-access memory.

4. The semiconductor device of claim 3, wherein the second transistor is a transistor of a read port of the static random-access memory.

5. The semiconductor device of claim 4, wherein the threshold voltage of the first transistor is higher than the threshold voltage of the second transistor.

6. The semiconductor device of claim 1, wherein each of the gates of the first transistor and the second transistor comprises:

a gate dielectric layer;

a work function layer on the gate dielectric layer; and

a metal layer on the work function layer.

7. The semiconductor device of claim 6, wherein a material of the work function layer of the gate of the first transistor adjacent to the metal layer is the same as the work function layer of the gate of the second transistor adjacent to the metal layer.

8. The semiconductor device of claim 1, wherein the third transistor comprises:

an active region; and

a gate disposed on the active region of the third transistor and separated from the gates of the first and second transistors.

9. A semiconductor device comprising:

a substrate having a first well and a second well that is spaced apart from the first well and that has the same conductivity type as the first well, the first well having a write region and a read region;

a first transistor disposed on the write region of the first well of the substrate and comprising;

an active region comprising a channel doping layer therein; and

a metal gate disposed on the active region of the first transistor; and

a second transistor disposed on the read region of the first well of the substrate and adjacent to the first transistor, wherein the second transistor comprises;

an active region; and

the metal gate disposed on the active region of the second transistor;

a third transistor disposed on the write region of the first well of the substrate, wherein the third transistor comprises a channel doping layer that has a doping concentration lower than a doping concentration of the channel doping layer of the first transistor; and

a fourth transistor disposed on the second well, wherein the fourth transistor comprises;

an active region; and

a metal gate disposed on the active region of the fourth transistor and separated from the metal gate of the first and second transistors.

10. The semiconductor device of claim 9, wherein the metal gate comprises:

a gate dielectric layer;

a work function layer on the gate dielectric layer; and

a metal layer on the work function layer.

11. The semiconductor device of claim 10, wherein a material of a portion of the work function layer disposed on the active region of the first transistor adjacent to the metal layer is the same as another portion of the work function layer disposed on the active region of the second transistor adjacent to the metal layer.

12. The semiconductor device of claim 9, wherein the active region of the second transistor comprises a channel doping layer, and a dopant concentration of the channel doping layer of the second transistor is less than a dopant concentration of the channel doping layer of the first transistor.

13. The semiconductor device of claim 9, wherein a dopant concentration of the channel doping layer of the first transistor is greater than a dopant concentration of the channel doping layer of the fourth transistor.

14. A semiconductor device comprising:

a first transistor disposed on a first well of a write portion of a substrate and comprising;

an active region comprising a channel doping layer therein; and

a metal gate disposed on the active region of the first transistor;

a second transistor disposed on a read portion of the substrate and adjacent to the first transistor, wherein the second transistor comprises;

an active region; and

the metal gate disposed on the active region of the second transistor,

wherein the first transistor and the second transistor have different threshold voltages, and the write portion of the substrate further includes a second well that is spaced from the first well and that has the same conductivity type as the first well and the channel doping layer of the first transistor has a doping concentration greater than doping concentrations of third and fourth transistors on the second well, wherein the fourth transistor comprises;

an active region; and

a metal gate disposed on the active region of the fourth transistor and separated from the metal gate of the first and second transistors; and

a fifth transistor disposed on the first well of the write region of the substrate, wherein the fifth transistor comprises a channel doping layer that has a doping concentration lower than a doping concentration of the channel doping layer of the first transistor.

15. The semiconductor device of claim 14, wherein the metal gate of the first and second transistors comprises:

a gate dielectric layer;

a work function layer on the gate dielectric layer; and

a metal layer on the work function layer.

16. The semiconductor device of claim 15, wherein a material of a portion of the work function layer disposed on the active region of the first transistor adjacent to the metal layer is the same as another portion of the work function layer disposed on the active region of the second transistor adjacent to the metal layer.

17. The semiconductor device of claim 14, wherein the active region of the second transistor comprises a channel doping layer, and a dopant concentration of the channel doping layer of the second transistor is less than a dopant concentration of the channel doping layer of the first transistor.

18. The semiconductor device of claim 14, wherein the first transistor is a transistor of a write port of a static random-access memory, wherein the second transistor is a transistor of a read port of the static random-access memory.

19. The semiconductor device of claim 18, wherein the threshold voltage of the first transistor is higher than the threshold voltage of the second transistor.

20. The semiconductor device of claim 14, wherein the third transistor on the second well comprises:

an active region having a channel doping layer; and

a metal gate disposed on the active region and separated from the metal gate of the first transistor and the second transistor.