Memory cell pillar including source junction plug

• US 10,515,972 B2
• Filed: 08/24/2017
• Issued: 12/24/2019
• Est. Priority Date: 11/07/2014
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Simsek-Ege, Fatma Arzum, Parat, Krishna K., Tran, Luan C., Kuo, Meng-Wei, Hu, Yushi
• Primary Examiner(s): Kim, Su C
• Application Number:
  US15/685,878
• Publication Number:
  US 20170373075A1
• Time in Patent Office: 852 Days
• CPC Class Codes: H01L 21/8221 Three dimensional integrated circuits stacked in different levels
• CPC Class Codes: H10B 41/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 41/35 with a cell select transistor, e.g. NAND
• CPC Class Codes: H10B 41/41 of a memory region comprising a cell select transistor, e.g. NAND
• CPC Class Codes: H10B 43/20 characterised by three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 43/23 with source and drain on different levels, e.g. with sloping channels
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/35 with cell select transistors, e.g. NAND

Abstract

Some embodiments include apparatuses and methods having a source material, a dielectric material over the source material, a select gate material over the dielectric material, a memory cell stack over the select gate material, a conductive plug located in an opening of the dielectric material and contacting a portion of the source material, and a channel material extending through the memory cell stack and the select gate material and contacting the conductive plug.

Claims

1. An apparatus comprising:

a material over a substrate;

a dielectric material over the material, the dielectric material including an opening;

a select gate material over the dielectric material;

memory cells over the select gate material, each of the memory cells including a charge-storage structure to store information;

an additional structure located in the opening of the dielectric material, the additional structure including a material portion, the material portion of the additional structure and the charge-storage structure having a same material, wherein the material portion is electrically separated from the substrate;

a channel material extending through the memory cells and the select gate material, the channel material including a bottom located above the material over the substrate; and

an additional dielectric material between the channel material and the select gate material, and the additional dielectric material directly contacting the channel material and the select gate material.

2. The apparatus of claim 1, wherein the charge-storage structure is polysilicon.

3. The apparatus of claim 1, wherein the charge-storage structure is silicon nitride.

4. The apparatus of claim 1, wherein the dielectric material includes a dielectric constant greater than a dielectric constant of silicon dioxide.

5. The apparatus of claim 1, wherein the material over the substrate includes conductively-doped polysilicon.

6. The apparatus of claim 1, further comprising a con e plug in the opening.

7. The apparatus of claim 1, further comprising silicon nitride between the channel material and the select gate material.

8. The apparatus of claim 7, further comprising silicon dioxide between the channel material and the select gate material.

9. The apparatus of claim 1, wherein the select gate material includes conductively-doped polysilicon.

10. The apparatus of claim 1, further comprising a second additional dielectric material surrounded by at least a portion of the channel material.

11. The apparatus of claim 1, further comprising a second additional dielectric material located in the opening.

12. The apparatus of claim 11, wherein the second additional dielectric material includes a dielectric constant greater than a dielectric constant of silicon dioxide.

13. An apparatus comprising:

a material over a substrate;

a dielectric material over the material, the dielectric material including a dielectric constant greater than a dielectric constant of silicon dioxide, the dielectric material including an opening;

a select gate material over the dielectric material;

memory cells over the select gate material;

a material portion in the opening, wherein the material portion is electrically separated from the substrate;

a conductive plug in the opening, the conductive plug located between the memory cells and the substrate;

a channel material extending through the memory cells and contacting the conductive plug; and

an additional dielectric material between the channel material and the select gate material, and the additional dielectric material directly contacting the channel material and the select gate material.

14. The apparatus of claim 13, wherein the conductive plug includes conductively-doped semiconductor material of n-type.

15. The apparatus of claim 13, wherein the conductive plug and the material over the substrate have a same material type.

16. The apparatus of claim 13, wherein the conductive plug has a thickness of at least one-half of a thickness of the dielectric material.

17. The apparatus of claim 13, further comprising a silicide material between the substrate and the material over the substrate.

18. A method comprising:

forming a material over a substrate;

forming a dielectric material over the material such that the dielectric material includes an opening;

forming a select gate material over the dielectric material;

forming memory cells over the select gate material, forming the memory cells including forming a charge-storage structure in each of the memory cells;

forming an additional structure in the opening of the dielectric material, the additional structure formed to have a same material as the charge-storage structure;

forming a material portion in the opening, wherein the material portion is electrically separated from the substrate;

forming a channel material extending through the memory cells and the select gate material, wherein the channel material is formed to include a bottom located above the material over the substrate; and

forming an additional dielectric material between the channel material and the select gate material, and the additional dielectric material directly contacting the channel material and the select gate material.

19. The method of claim 18, further comprising:

forming a conductive plug in the opening.

20. The method of claim 18, wherein the dielectric material includes aluminum oxide, hafnium silicate, zirconium silicate, hafnium dioxide, or zirconium dioxide.