Multilevel semiconductor device and structure with memory
First Claim
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1. A multilevel semiconductor device, the device comprising:
- a first level comprising a first array of first memory cells and a first control line;
a second level comprising a second array of second memory cells and a second control line;
a third level comprising a third array of third memory cells and a third control line,wherein said second level overlays said first level, andwherein said third level overlays said second level;
a first access pillar;
a second access pillar; and
a third access pillar,wherein said first memory cells are self-aligned to said second memory cells,wherein said first access pillar has a first electrically programmable connection to said first control line,wherein said second access pillar has a second electrically programmable connection to said second control line, andwherein said third access pillar has a third electrically programmable connection to said third control line.
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Abstract
A multilevel semiconductor device, the device including: a first level including a first array of first programmable cells and a first control line; a second level including a second array of second programmable cells and a second control line; and a third level including a third array of third programmable cells and a third control line, where the second level overlays the first level, where the third level overlays the second level, where the first programmable cells are self-aligned to the second programmable cells, and where a programmable logic cell includes a plurality of the first programmable cells and a plurality of the second programmable cells.
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Citations
20 Claims
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1. A multilevel semiconductor device, the device comprising:
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a first level comprising a first array of first memory cells and a first control line; a second level comprising a second array of second memory cells and a second control line; a third level comprising a third array of third memory cells and a third control line, wherein said second level overlays said first level, and wherein said third level overlays said second level; a first access pillar; a second access pillar; and a third access pillar, wherein said first memory cells are self-aligned to said second memory cells, wherein said first access pillar has a first electrically programmable connection to said first control line, wherein said second access pillar has a second electrically programmable connection to said second control line, and wherein said third access pillar has a third electrically programmable connection to said third control line. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A multilevel semiconductor device, the device comprising:
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a first level comprising a first array of first programmable cells and a first control line; a second level comprising a second array of second programmable cells and a second control line; and a third level comprising a third array of third programmable cells and a third control line, wherein said second level overlays said first level, wherein said third level overlays said second level, wherein said first programmable cells are self-aligned to said second programmable cells, and wherein a programmable logic cell comprises a plurality of said first programmable cells and a plurality of said second programmable cells. - View Dependent Claims (9, 10, 11, 12, 13, 14)
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15. A multilevel semiconductor device, the device comprising:
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a first level comprising a first array of first memory cells and a first control line; a second level comprising a second array of second memory cells and a second control line; a third level comprising a third array of third memory cells and a third control line, wherein said second level overlays said first level, and wherein said third level overlays said second level; a first access pillar; a second access pillar; a third access pillar; and a memory control level comprising memory control circuits designed to individually control every cell of said first memory cells, second memory cells and third memory cells, wherein said memory control level overlays said third level or underlays said first level, wherein said device comprises an array of units, wherein each of said units comprises a plurality of said first memory cells, said second memory cells, said third memory cells, and a portion of said memory control circuits, wherein said array of units comprise at least four rows and four columns of units, and wherein said memory control circuits are designed to control independently each of said units. - View Dependent Claims (16, 17, 18, 19, 20)
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Specification
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Current AssigneeMonolithic 3D, Inc.
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Original AssigneeMonolithic 3D, Inc.
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InventorsOr-Bach, Zvi, Han, Jin-Woo
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Primary Examiner(s)Campbell, Shaun M
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Assistant Examiner(s)Chi, Suberr L
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Application NumberUS15/761,426Publication NumberTime in Patent Office1,189 DaysField of SearchUS Class CurrentCPC Class CodesB82Y 10/00 Nanotechnology for informat...H01L 2027/11838 Implementation of memory fu...H01L 2027/11888 More than 3 levels of metalH01L 27/11807 CMOS gate arraysH01L 29/0673 oriented parallel to a subs...H01L 29/40117 the electrodes comprising a...H01L 29/42392 fully surrounding the chann...H01L 29/66439 with a one- or zero-dimensi...H01L 29/775 with one dimensional charge...H01L 29/7889 Vertical transistors, i.e. ...H10B 43/20 characterised by three-dime...H10B 63/20 comprising selection compon...H10B 63/34 of the vertical channel fie...H10B 63/845 the switching components be...
