×

Multilevel semiconductor device and structure with memory

  • US 10,515,981 B2
  • Filed: 09/21/2016
  • Issued: 12/24/2019
  • Est. Priority Date: 09/21/2015
  • Status: Expired due to Fees
First Claim
Patent Images

1. A multilevel semiconductor device, the device comprising:

  • a first level comprising a first array of first memory cells and a first control line;

    a second level comprising a second array of second memory cells and a second control line;

    a third level comprising a third array of third memory cells and a third control line,wherein said second level overlays said first level, andwherein said third level overlays said second level;

    a first access pillar;

    a second access pillar; and

    a third access pillar,wherein said first memory cells are self-aligned to said second memory cells,wherein said first access pillar has a first electrically programmable connection to said first control line,wherein said second access pillar has a second electrically programmable connection to said second control line, andwherein said third access pillar has a third electrically programmable connection to said third control line.

View all claims
  • 1 Assignment
Timeline View
Assignment View
    ×
    ×