Metal-insulator-semiconductor-insulator-metal (MISIM) device, method of operation, and memory device including the same

• US 10,515,998 B2
• Filed: 06/13/2018
• Issued: 12/24/2019
• Est. Priority Date: 09/29/2017
• Status: Active Grant

• Current Assignee: National Taiwan University (Government of The Republic of China), Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Hwu, Jenn-Gwo, Lin, Hao-Hsiung, Yan, Chang-Feng, Pan, Samuel C.
• Primary Examiner(s): Le, Thong Q
• Application Number:
  US16/007,678
• Publication Number:
  US 20190103441A1
• Time in Patent Office: 559 Days
• Field of Search: 257E33008, 257 13, 257 40, 257 53, 257E29058, 257E29233, 257216, 257217, 257245, 257250, 257 4, 257 42, 257428, 257 43, 257 49, 438382, 438 59, 438 31, 438 46, 365148, 365 63
• CPC Class Codes: G11C 11/34 using semiconductor devices
• CPC Class Codes: G11C 11/56 using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
• CPC Class Codes: G11C 13/0007 comprising metal oxide memory material, e.g. perovskites
• CPC Class Codes: H01L 29/417 carrying the current to be rectified, amplified or switched
• CPC Class Codes: H01L 29/88 Tunnel-effect diodes
• CPC Class Codes: H10B 99/00 Subject matter not provided for in other groups of this subclass
• CPC Class Codes: H10N 80/10 Gunn-effect devices
• CPC Class Codes: H10N 89/02 Gunn-effect integrated devices

Abstract

A metal-insulator-semiconductor-insulator-metal (MISIM) device includes a semiconductor layer, an insulating layer disposed over an upper surface of the semiconductor layer, a back electrode disposed over a lower surface of the semiconductor layer opposing the upper surface, and first and second electrodes disposed over the insulating layer and spaced-apart from each other.

Claims

1. A metal-insulator-semiconductor-insulator-metal (MISIM) device, comprising:

a semiconductor layer;

an insulating layer disposed over an upper surface of the semiconductor layer;

a back electrode disposed over a lower surface of the semiconductor layer opposing the upper surface; and

first and second electrodes disposed over the insulating layer and spaced-apart from each other,

wherein the first electrode has a circular shape and the second electrode has a ring shape surrounding the first electrode.

2. The MISIM device of claim 1, wherein a thickness of the insulating layer is 1 nm to 4 nm.

3. The MISIM device of claim 1, wherein the semiconductor layer is an N-type semiconductor, and the first electrode and the second electrode are made of a material having a flatband voltage V_FB greater than 0.

4. The MISIM device of claim 3, wherein the N-type semiconductor material has a doping concentration of 5·

10¹⁴/cm<sup>−

3</sup> to 5·

10¹⁷/cm<sup>−

3</sup>.

5. The MISIM device of claim 1, wherein the semiconductor layer is a P-type semiconductor, and the first electrode and the second electrode are made of a material having a flatband voltage V_FB less than 0.

6. The MISIM device of claim 5, wherein the P-type semiconductor material has a doping concentration of 5·

10¹⁴/cm<sup>−

3</sup> to 5·

10¹⁷/cm<sup>−

3</sup>.

7. The MISIM device of claim 1, further comprising a substrate,

wherein the back electrode is disposed between the semiconductor layer and the substrate.

8. The MISIM device of claim 1, wherein the first electrode has a diameter ranging from 100 nm to 400 nm, and the second electrode has an inner diameter ranging from 110 nm to 460 nm.

9. The MISIM device of claim 1, wherein the first electrode has a diameter ranging from 200 nm to 20 μ

m, and the second electrode has an inner diameter ranging from 400 nm to 50 μ

m.

10. The MISIM device of claim 1, wherein the first electrode and the second electrode are made of aluminum, hafnium, magnesium, or an alloy thereof.

11. The MISIM device of claim 1, wherein the back electrode is made of aluminum, gold, titanium, polysilicon, silver, nickel, copper, or a mixture thereof.

12. A memory device including a plurality of cells coupled to a plurality of wordlines and a plurality of bitlines, wherein

each cell includes the MISIM device of claim 1, a resistor, and a pass-gate transistor, a gate electrode of the pass-gate transistor connected to one of the plurality of wordlines and a source of the pass-gate transistor connected to one of the plurality of bitlines, and

in each cell:

the second electrode of the MISIM device is connected to the ground;

a bias voltage source provides a bias between the first electrode and the back electrode of the MISIM device;

the first electrode of the MISIM device and one end of the resistor are connected to a drain of the pass-gate transistor; and

a constant current source connects another end of the resistor to the ground.

13. A memory device including a plurality of cells coupled to a plurality of wordlines and a plurality of bitlines, wherein

each cell includes the MISIM device of claim 1, a resistor, and a pass-gate transistor, a gate electrode of the pass-gate transistor connected to one of the plurality of wordlines and a source of the pass-gate transistor connected to one of the plurality of bitlines, and

in each cell:

the back electrode of the MISIM device is connected to the ground;

a bias voltage source provides a bias between the first electrode and the second electrode of the MISIM device;

the first electrode of the MISIM device and one end of the resistor are connected to a drain of the pass-gate transistor; and

a constant current source connects another end of the resistor to the ground.

14. A memory device including first and second cells cross-coupled to each other, wherein

the first and second cells each include the MISIM device of claim 1,

the back electrodes of the MISIM devices of the first and second cells are connected to the ground,

the second electrode of the MISIM of the first cell and the first electrode of the MISIM of the second cell are coupled to each other, and are connected to a first bitline through a first pass-gate transistor,

the first electrode of the MISIM of the first cell and the second electrode of the MISIM of the second cell are coupled to each other, and are connected to a second bitline through a second pass-gate transistor, and

gate electrodes of the first and second pass-gate transistors are respectively connected to first and second wordlines.

15. A method for operating a metal-insulator-semiconductor-insulator-metal (MISIM) device, wherein the MISIM device includes a semiconductor layer, an insulating layer disposed over an upper surface of the semiconductor layer, a back electrode disposed over a lower surface of the semiconductor layer opposing the upper surface, and first and second electrodes disposed over the insulating layer and spaced-apart from each other, the method comprising:

increasing a voltage difference between the first electrode and the second electrode from a first value to a second value or decreasing the voltage difference between the first electrode and the second electrode from the second value to the first value, while maintaining connection of the second electrode and the ground and maintaining a bias between the first electrode and the back electrode.

16. The method of claim 15, wherein the bias is a constant.

17. The method of claim 15, wherein current passing through the first electrode of the MISIM has a peak when increasing the voltage difference between the first electrode and the second electrode from the first value to the second value or decreasing the voltage difference between the first electrode and the second electrode from the second value to the first value.

18. A method for operating a metal-insulator-semiconductor-insulator-metal (MISIM) device, wherein the MISIM device includes a semiconductor layer, an insulating layer disposed over an upper surface of the semiconductor layer, a back electrode disposed over a lower surface of the semiconductor layer opposing the upper surface, and first and second electrodes disposed over the insulating layer and spaced-apart from each other, the method comprising:

increasing a voltage difference between the first electrode and the back electrode from a first value to a second value or decreasing the voltage difference between the first electrode and the back electrode from the second value to the first value, while maintaining connection of the back electrode and the ground and maintaining a bias between the first electrode and the second electrode.

19. The method of claim 18, wherein the bias is a constant.

20. The method of claim 18, wherein current passing through the first electrode of the MISIM has two peaks when increasing the voltage difference between the first electrode and the back electrode from the first value to the second value or decreasing the voltage difference between the first electrode and the back electrode from the second value to the first value.