Spacer structure with high plasma resistance for semiconductor devices

• US 10,516,036 B1
• Filed: 09/19/2019
• Issued: 12/24/2019
• Est. Priority Date: 09/29/2017
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Kao, Wan-Yi, Ko, Chung-Chi
• Primary Examiner(s): Dulka, John P.
• Application Number:
  US16/575,974
• Publication Number:
  US 20200013872A1
• Time in Patent Office: 96 Days
• CPC Class Codes: H01L 21/28132 conducting part of electrode is difined by a sidewall spacer or a similar technique, e.g. oxidation under mask, plating
• CPC Class Codes: H01L 21/823431 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823821 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823828 with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 21/823864 with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
• CPC Class Codes: H01L 27/0886 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/0924 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/1033 with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with channel and gate aligned in the lengthwise direction H01L29/42376; with buried channel H01L29/7838
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66553 using inside spacers, permanent or not
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/66719 With a step of forming an insulating sidewall spacer
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

Semiconductor device structures comprising a spacer feature having multiple spacer layers are provided. In one example, a semiconductor device includes an active area on a substrate, the active area comprising a source/drain region, a gate structure over the active area, the source/drain region being proximate the gate structure, a spacer feature having a first portion along a sidewall of the gate structure and having a second portion along the source/drain region, wherein the first portion of the spacer feature comprises a bulk spacer layer along the sidewall of the gate structure, wherein the second portion of the spacer feature comprises the bulk spacer layer and a treated seal spacer layer, the treated seal spacer layer being disposed along the source/drain region and between the bulk spacer layer and the source/drain region, and a contact etching stop layer on the spacer feature.

Claims

1. A method for forming a semiconductor device, comprising:

forming a dummy gate on a fin, the fin protruding from a substrate;

forming a first spacer layer over the dummy gate and the fin, the first spacer layer having a first density;

treating the first spacer layer to form a treated first spacer layer, the treated first spacer layer having a second density, the second density being greater than the first density;

forming a second spacer layer on the treated first spacer layer;

anisotropically etching the second spacer layer and the treated first spacer layer to form a spacer structure along sidewalls of the dummy gate and sidewalls of the fin, the spacer structure comprising portions of the treated first spacer layer and portions of the second spacer layer; and

replacing the dummy gate with a replacement gate, wherein the portions of the treated first spacer layer is interposed between the second spacer layer and the fin, wherein replacing the dummy gate comprises removing at least some of the treated first spacer layer along sidewalls of the second spacer layer.

2. The method of claim 1, wherein forming the first spacer layer comprises an atomic layer deposition process, the atomic layer deposition process comprising:

flowing a first precursor into a process chamber, the first precursor being a silicon and carbon source precursor;

purging the process chamber; and

flowing a second precursor into the process chamber, the second precursor being an oxygen source precursor.

3. The method of claim 1, wherein the first spacer layer has a dielectric constant from about 3.2 to about 3.7.

4. The method of claim 3, wherein the treated first spacer layer has a dielectric constant a range from about 3.5 to about 3.9.

5. The method of claim 1, wherein treating the first spacer layer comprises a plasma process using a hydrogen containing gas.

6. The method of claim 1, wherein a dielectric constant of the first spacer layer is greater than a dielectric constant of the treated first spacer layer.

7. A method for forming a semiconductor device, comprising:

forming a fin and isolation regions on a substrate, wherein the fin extends above the isolation regions, wherein the fin is interposed between the isolation regions;

forming a dummy gate over the fin and the isolation regions;

forming a seal spacer layer over the dummy gate, the isolation regions, and the fin, the seal spacer layer extending along opposing sidewalls of the fin, the seal spacer layer having a first density and a first dielectric constant;

treating the seal spacer layer with a plasma to form a treated seal spacer layer, the treated seal spacer layer having a second density and a second dielectric constant, the second density being greater than the first density, the second dielectric constant being lower than the first dielectric constant;

forming a bulk spacer layer on the treated seal spacer layer;

patterning the bulk spacer layer and the treated seal spacer layer to form a bulk spacer and a treated seal spacer, respectively, along sidewalls of the dummy gate, the treated seal spacer being interposed between the treated seal spacer and the fin, an upper surface of the dummy gate being exposed after patterning;

removing the dummy gate exposing sidewalls of the treated seal spacer, thereby forming a recess between opposing sidewalls of the treated seal spacer; and

forming a gate structure in the recess.

8. The method of claim 7, wherein the seal spacer layer is a carbon-containing layer.

9. The method of claim 7, wherein the seal spacer layer has a thickness in a range from 20 Å

to 35 Å

.

10. The method of claim 7, wherein the treated seal spacer layer has a greater roughness than the seal spacer layer.

11. The method of claim 10, wherein the treated seal spacer layer has a surface roughness in a range from about 6 Å

to about 60 Å

.

12. The method of claim 7, wherein a thickness of the treated seal spacer layer is in a range from about 10% to 20% less than the thickness of the seal spacer layer.

13. The method of claim 7, wherein a density of the seal spacer layer is 1.7, wherein a density of the treated seal spacer layer is 2.5.

14. The method of claim 7, wherein a thickness of the bulk spacer layer is greater than a thickness of the treated seal spacer layer.

15. The method of claim 7, wherein the seal spacer layer and the bulk spacer layer are formed of a same material.

16. A semiconductor device, comprising:

a fin protruding from a substrate;

isolation regions along opposing sides of the fin;

a gate structure over the fin and the isolation regions; and

a first spacer structure and a second spacer structure on the fin, the gate structure being interposed between the first spacer structure and the second spacer structure, each of the first spacer structure and the second spacer structure comprising a treated seal spacer and a bulk spacer on the treated seal spacer, the treated seal spacer being disposed between the bulk spacer and the fin, wherein the bulk spacer has a lower dielectric constant than the treated seal spacer.

17. The semiconductor device of claim 16, wherein a thickness of the bulk spacer is greater than a thickness of the treated seal spacer.

18. The semiconductor device of claim 16, wherein the treated seal spacer and the bulk spacer are formed of a same material.

19. The semiconductor device of claim 16, wherein the treated seal spacer and the bulk spacer comprise SiOC.

20. The semiconductor device of claim 16, wherein the bulk spacer has a lower density than the treated seal spacer.