Method of forming shaped source/drain epitaxial layers of a semiconductor device

• US 10,516,037 B2
• Filed: 11/01/2017
• Issued: 12/24/2019
• Est. Priority Date: 06/30/2017
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Lee, Yi-Jing, Yu, Ming-Hua
• Primary Examiner(s): Smith, Zandra V
• Assistant Examiner(s): Parker, John M
• Application Number:
  US15/801,097
• Publication Number:
  US 20190006491A1
• Time in Patent Office: 783 Days
• CPC Class Codes: H01L 21/02381 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02576 N-type
• CPC Class Codes: H01L 21/02609 Crystal orientation
• CPC Class Codes: H01L 21/0262 Reduction or decomposition of gaseous compounds, e.g. CVD
• CPC Class Codes: H01L 21/02639 Preparation of substrate for selective deposition
• CPC Class Codes: H01L 21/3065 Plasma etching; Reactive-ion etching
• CPC Class Codes: H01L 21/823814 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/823821 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/0924 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/045 by their particular orientation of crystalline planes
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

In a method for manufacturing a semiconductor device, an isolation insulating layer is formed over a fin structure. A first portion of the fin structure is exposed from and a second portion of the fin structure is embedded in the isolation insulating layer. A dielectric layer is formed over sidewalls of the first portion of the fin structure. The first portion of the fin structure and a part of the second portion of the fin structure in a source/drain region are removed, thereby forming a trench. A source/drain epitaxial structure is formed in the trench using one of a first process or a second process. The first process comprises an enhanced epitaxial growth process having an enhanced growth rate for a preferred crystallographic facet, and the second process comprises using a modified etch process to reduce a width of the source/drain epitaxial structure.

Claims

1. A method for manufacturing a semiconductor device, comprising:

forming an isolation insulating layer over a fin structure, wherein a first portion of the fin structure is exposed from the isolation insulating layer and a second portion of the fin structure is embedded in the isolation insulating layer;

forming a gate structure over a part of the first portion of the fin structure;

forming a dielectric layer over sidewalls of the first portion of the fin structure in a source/drain region not covered by the gate structure;

removing the first portion of the fin structure and a part of the second portion of the fin structure between portions of the dielectric layer in the source/drain region, thereby forming a trench over a remaining part of the second portion of the fin structure and between the portions of the dielectric layer that extend along an entire length of the trench; and

forming a source/drain (SD) epitaxial structure in the trench using one of a first process or a second process,

wherein a top surface of the remaining part of the second portion of the fin structure in the trench provides a preferred crystallographic facet, and the first process comprises an enhanced epitaxial growth process having an enhanced growth rate for the preferred crystallographic facet,

the second process comprises disposing an SD epitaxial structure in the trench and on top of the trench and using a modified etch process to reduce a width of the SD epitaxial structure on top of the trench, and

after either of the first process or the second process a lateral extent of the SD epitaxial structure on top of the trench is limited to about sidewalls of the portions of the dielectric layer that are further away from the trench.

2. The method of claim 1, wherein the preferred crystallographic facet comprise a (100) facet, and wherein an epitaxial deposition is performed with an enhanced growth ratio on facet (100) over facet (111) and on facet (100) over facet (110), wherein the enhanced growth ratio is between 3 to 5 times.

3. The method of claim 1, wherein the semiconductor device comprises an NMOS device, and wherein the first process is performed using a chemical vapor deposition (CVD) process.

4. The method of claim 3, wherein the CVD process is performed at a high temperature within a range of about 650-700°

C. and a pressure within a range of about 200-350 Torr.

5. The method of claim 1, wherein the semiconductor device comprises a PMOS device, and wherein the first process is performed using a CVD process at a high temperature within a range of about 600-650°

C. and a pressure within a range of about 5-50 Torr.

6. The method of claim 1, wherein the semiconductor device comprises an NMOS device, and wherein the modified etch process comprises a CVD etch operation.

7. The method of claim 6, wherein the CVD etch operation is performed using a mixture of germanium tetrahydride (GeH₄) and hydrochloric acid (HCl) with a GeH₄ to HCl mixture ratio within a range of about 0.5-1.2 and at a high temperature within a range of about 650-750°

C. and a pressure within a range of about 5-100 Torr.

8. The method of claim 6, wherein the CVD etch operation is performed using a mixture of silicon tetrahydride (SiH₄) and HCl with a SiH₄ to HCl mixture ratio within a range of about 0.2-0.25 and at a high temperature within a range of about 650-750°

C. and a pressure within a range of about 5-100 Torr.

9. The method of claim 1, wherein the semiconductor device comprises a PMOS device, and wherein the modified etch process comprises a CVD etch operation using HCl at a flow rate within a range of about 50-120 sccm, a temperature within a range of about 600-650°

C., and a pressure within a range of about 5-50 Torr.

10. The method of claim 1, wherein the isolation insulating layer comprises a shallow trench isolation (STI) material, and wherein the dielectric layer comprises silicon nitride (Si₃N₄), silicon oxide (SiO₂), or silicon oxynitride (SiO_xN_y), and wherein the dielectric layer over the sidewalls of the first portion of the fin structure is asymmetric and results in an asymmetry of the SD epitaxial structure formed by the enhanced epitaxial growth process.

11. A method for manufacturing a semiconductor device, comprising:

forming a first structure extending in a first direction, the first structure including a fin made of a first material and having a first portion exposed and a second portion embedded;

forming a gate structure over a part of the first portion of the fin;

forming a dielectric layer over sidewalls of the first portion of the fin in a source/drain region not covered by the gate structure;

removing the first material from the first portion and a part of the second portion of the fin between portions of the dielectric layer in the source/drain region, thereby forming a trench over a remaining part of the second portion of the fin and between the portions of the dielectric layer that extend along an entire length of the trench;

forming in and above the trench a source/drain (SD) epitaxial structure; and

performing an modified etch process to partially remove portions of a top part of the SD epitaxial structure grown in a second direction perpendicular to the first direction, thereby producing flat sides on the top part of the epitaxial structure,

wherein after the modified etch process an extent of the top part of the SD epitaxial structure in the second direction is limited to about sidewalls of the portions of the dielectric layer that are further away from the trench.

12. The method of claim 11, wherein the first structure includes an isolation insulating layer deposited on the second portion of the fin, and wherein the first material comprises a substrate material.

13. The method of claim 11, wherein the semiconductor device comprises an NMOS device, and wherein the modified etch process comprises a CVD etch operation.

14. The method of claim 13, wherein performing the CVD etch operation comprises using a mixture of GeH₄ and HCl with a GeH₄ to HCl mixture ratio within a range of about 0.5-1.2.

15. The method of claim 14, wherein the CVD etch operation is performed at a temperature within a range of about 650-750°

C. and a pressure within a range of about 5-100 Torr.

16. The method of claim 13, wherein performing the CVD etch operation comprises using a mixture of silicon tetrahydride (SiH₄) and HCl with a SiH₄ to HCl mixture ratio within a range of about 0.2-0.25.

17. The method of claim 16, wherein the CVD etch operation is performed at a temperature within a range of about 650-750°

C. and a pressure within a range of about 5-100 Torr.

18. The method of claim 11, wherein the semiconductor device comprises a PMOS device, and wherein the modified etch process comprises a CVD etch operation using HCl at a flow rate within a range of about 50-120 sccm.

19. The method of claim 18, wherein the CVD etch operation is performed at a temperature within a range of about 600-650°

C. and a pressure within a range of about 5-50 Torr.

20. A method for manufacturing a semiconductor device, comprising:

forming a first structure extending in a first direction, the first structure including a fin made of a first material and having a first portion exposed and a second portion embedded;

forming a gate structure over a part of the first portion of the fin;

forming a dielectric layer over sidewalls of the first portion of the fin in a source/drain region not covered by the gate structure;

removing the first material from the first portion and a part of the second portion of the fin between portions of the dielectric layer in the source/drain region, thereby forming a trench over a remaining part of the second portion of the fin and between the portions of the dielectric layer that extend along an entire length of the trench;

forming in and above the trench a source/drain (SD) epitaxial structure; and

performing a modified etch process to partially remove portions of a top part of the epitaxial structure grown in a second direction perpendicular to the first direction, thereby producing a diamond-shape top for the SD epitaxial structure with flat side surfaces parallel to the first direction,

wherein after the modified etch process an extent of the top part of the SD epitaxial structure in the second direction is limited to about sidewalls of the portions of the dielectric layer that are further away from the trench.