Multi-gate device and method of fabrication thereof

• US 10,516,049 B2
• Filed: 11/10/2017
• Issued: 12/24/2019
• Est. Priority Date: 06/30/2015
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Ching, Kuo-Cheng, Tsai, Ching-Wei, Diaz, Carlos H., Wang, Chih-Hao, Lien, Wai-Yi, Leung, Ying-Keung
• Primary Examiner(s): Huber, Robert T
• Assistant Examiner(s): Swan, Gardner W. S.
• Application Number:
  US15/809,726
• Publication Number:
  US 20180090615A1
• Time in Patent Office: 774 Days
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/0673 oriented parallel to a substrate
• CPC Class Codes: H01L 29/0676 oriented perpendicular or at an angle to a substrate
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/42392 fully surrounding the channel, e.g. gate-all-around
• CPC Class Codes: H01L 29/66439 with a one- or zero-dimensional channel, e.g. quantum wire FET, in-plane gate transistor [IPG], single electron transistor [SET], striped channel transistor, Coulomb blockade transistor with an active layer made of a group 13/15 material H01L29/66469
• CPC Class Codes: H01L 29/66537 using a self aligned punch through stopper or threshold implant under the gate region H01L29/66606 takes precedence
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/775 with one dimensional charge carrier gas channel, e.g. quantum wire FET
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain
• CPC Class Codes: H01L 29/7851 with the body tied to the substrate
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

A method of semiconductor device fabrication is described that includes forming a fin extending from a substrate and having a source/drain region and a channel region. The fin includes a first epitaxial layer having a first composition and a second epitaxial layer on the first epitaxial layer, the second epitaxial layer having a second composition. The second epitaxial layer is removed from the source/drain region of the fin to form a gap. The gap is filled with a dielectric material. Another epitaxial material is formed on at least two surfaces of the first epitaxial layer to form a source/drain feature.

Claims

1. A method of semiconductor device fabrication, comprising:

forming a fin extending from a substrate, the fin having a source/drain region and a channel region, wherein the fin includes a first epitaxial layer having a first composition and a second epitaxial layer on the first epitaxial layer, the second epitaxial layer having a second composition, and a third epitaxial layer having the first composition over the second epitaxial layer wherein the forming the fin further includes forming an oxidized epitaxial layer that is disposed in the channel region and the source/drain region, wherein the oxidized epitaxial layer underlies the first source/drain feature;

forming a dummy gate structure over the channel region of the fin;

after forming the dummy gate structure, removing the second epitaxial layer from the source/drain region of the fin to form a gap extending from the first epitaxial layer to the third epitaxial layer;

depositing a spacer layer on sidewalls of the dummy gate structure and filling the gap such that a dielectric material of the spacer layer extends continuously from a top surface of the first epitaxial layer to a bottom surface of the third epitaxial layer and continuously along a length of source/drain region; and

while the spacer layer is filled within the gap, growing a source/drain epitaxial material on at least two surfaces of the first epitaxial layer to form a first source/drain feature on the fin.

2. The method of claim 1,

wherein the forming the oxidized epitaxial layer includes:

prior to forming the first epitaxial layer, forming another epitaxial layer underlying the first epitaxial layer; and

oxidizing the another epitaxial layer to form an oxidized another epitaxial layer; and

wherein the oxidized another epitaxial layer underlies a gate on the channel region and the first source/drain feature.

3. The method of claim 2, wherein the oxidized another epitaxial layer is thicker than the first epitaxial layer.

4. The method of claim 1, further comprising:

after growing the source/drain epitaxial material, removing the dummy gate structure to form a trench exposing the channel region of the fin;

removing the second epitaxial layer from the channel region of the fin to from another gap; and

forming a gate structure on the first epitaxial layer in the channel region, wherein at least a portion of the gate structure is formed in the another gap.

5. The method of claim 1, wherein the depositing the spacer layer includes depositing silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, SiCN films, silicon oxycarbide, SiOCN films, or combinations thereof.

6. The method of claim 1, further comprising:

forming the first epitaxial layer by growing a silicon layer; and

forming the second epitaxial layer by growing a silicon germanium layer directly on the silicon layer.

7. The method of claim 1, further comprising:

after the depositing the spacer layer, etching back the spacer layer to remove the spacer layer from sidewalls of the first epitaxial layer and the third epitaxial layer.

8. The method of claim 1, wherein the spacer layer filling the gap extends under spacer elements abutting the sidewalls of the dummy gate structure.

9. The method of claim 1, wherein the growing the source/drain epitaxial material further comprises growing a source/drain material on at least two surfaces of the third epitaxial layer.

10. The method of claim 9, wherein the source/drain epitaxial material grown on the first epitaxial layer is separated from the source/drain epitaxial material grown on the third epitaxial layer.

19. The method of claim 1, wherein the oxidized epitaxial layer includes an oxide of silicon germanium.

20. The method of claim 1, further comprising:

after forming the first source/drain feature, forming a gate structure, wherein oxidized epitaxial layer underlies the gate structure.

11. A method of fabricating a multi-gate device, the method comprising:

forming a bottom epitaxial layer;

growing an epitaxial layer stack including first, second, and third epitaxial layers over the bottom epitaxial layer;

oxidizing the bottom epitaxial layer to form an oxide layer;

removing the second epitaxial layer in a first region and a second region of the epitaxial layer stack to form a space between the first and third epitaxial layers;

depositing a dielectric material in the space, wherein the first and second regions are interposed by a third region of the epitaxial layer stack, wherein the third region underlies a dummy gate structure, wherein a thickness of the oxide layer is greater than the thickness of the dielectric material; and

forming a metal gate structure disposed on multiple sides of each of the first and third epitaxial layers in the third region of the epitaxial layer stack.

12. The method of claim 11, wherein the forming the metal gate structure includes forming a high-k dielectric layer of the metal gate structure on multiple sides of each of the first and third epitaxial layers.

13. The method of claim 11, wherein the depositing the dielectric material in the space includes depositing a blanket layer of the dielectric material and etching back the blanket layer.

14. The method of claim 11, further comprising:

growing an epitaxial cladding on the first epitaxial layer in the first region and the second region.

15. The method of claim 14, further comprising:

growing another epitaxial cladding on the third epitaxial layer in the first region and the second region.

16. A method of semiconductor device fabrication, comprising:

forming a fin extending from a substrate, the fin including a first epitaxial layer having a first composition and a second epitaxial layer on the first epitaxial layer, the second epitaxial layer having a second composition, and a third epitaxial layer having the first composition over the second epitaxial layer;

removing the second epitaxial layer from a source/drain region of the fin to form a first gap extending from the first epitaxial layer to the third epitaxial layer while protecting a channel region of the fin;

depositing a dielectric material within the first gap, wherein the depositing the dielectric material within the first gap includes;

depositing a blanket layer of the dielectric material over a top surface of the third epitaxial layer, and

etching the blanket layer to remove the dielectric material from the top surface of the third epitaxial layer and remove the dielectric material from a portion of a top surface of the first epitaxial layer;

while the dielectric material is within the first gap, growing a source/drain epitaxial material on at least two surfaces of the first epitaxial layer to form a first source/drain feature on the fin;

while the dielectric material is within the first gap, forming an interlayer dielectric (ILD) layer over the source/drain epitaxial material;

providing a trench in the ILD layer to expose the channel region of the fin; and

removing the second epitaxial layer within the trench to provide a second gap.

17. The method of claim 16, further comprising:

after removing the second epitaxial layer within the trench, depositing a gate structure in the second gap.

18. The method of claim 17, wherein the depositing the gate structure in the second gap includes depositing a gate dielectric layer to fill the second gap.