Method for forming stressor, semiconductor device having stressor, and method for forming the same

• US 10,516,050 B2
• Filed: 03/09/2017
• Issued: 12/24/2019
• Est. Priority Date: 07/29/2016
• Status: Active Grant

• Current Assignee: National Taiwan University (Government of The Republic of China), Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Yang, Che-Wei, Lin, Hao-Hsiung, Pan, Samuel C.
• Primary Examiner(s): Prenty, Mark V
• Application Number:
  US15/454,118
• Publication Number:
  US 20180033889A1
• Time in Patent Office: 1,020 Days
• CPC Class Codes: H01L 21/02381 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02546 Arsenides
• CPC Class Codes: H01L 21/02603 Nanowires
• CPC Class Codes: H01L 21/02639 Preparation of substrate for selective deposition
• CPC Class Codes: H01L 21/26506 in group IV semiconductors
• CPC Class Codes: H01L 21/324 Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering H01L21/20 - H01L21/288 and H01L21/302 - H01L21/322 take precedence
• CPC Class Codes: H01L 29/0676 oriented perpendicular or at an angle to a substrate
• CPC Class Codes: H01L 29/1037 and non-planar channel resulting from the gate electrode disposition, e.g. within a trench, H01L29/42356
• CPC Class Codes: H01L 29/1054 with a variation of the composition, e.g. channel with strained layer for increasing the mobility
• CPC Class Codes: H01L 29/20 including, apart from doping materials or other impurities, only AIIIBV compounds
• CPC Class Codes: H01L 29/267 in different semiconductor regions , e.g. heterojunctions H01L29/263 takes precedence
• CPC Class Codes: H01L 29/36 characterised by the concentration or distribution of impurities in the bulk material within semiconductor regions H01L29/06
• CPC Class Codes: H01L 29/66522 with an active layer made of a group 13/15 material H01L29/66446 takes precedence
• CPC Class Codes: H01L 29/66568 Lateral single gate silicon transistors
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7842 means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate variation of the composition of the channel H01L29/1054
• CPC Class Codes: H01L 29/7843 the means being an applied insulating layer
• CPC Class Codes: H01L 29/7849 the means being provided under the channel
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

A semiconductor device includes a semiconductor fin protruding from a substrate, a gate electrode over the semiconductor fin, a gate insulating layer between the semiconductor fin and the gate electrode, source and drain regions disposed on opposite sides of the semiconductor fin, a first stressor formed in a region between the source and drain regions. The first stressor including one material selected from the group consisting of He, Ne, and Ga.

Claims

1. A method for manufacturing a semiconductor device, the method comprising:

forming a gate structure comprising;

forming a semiconductor fin on a substrate;

forming a gate insulating layer to cover the semiconductor fin; and

forming a gate electrode layer to cover the gate insulating layer;

forming a first stressor in the substrate by an ion beam, wherein the first stressor is formed on one side of the semiconductor fin;

forming a second stressor in the substrate on another side of the semiconductor fin opposite to the first stressor with respect to the semiconductor fin; and

forming source and drain regions on opposite sides of the gate structure, wherein the first stressor and the second stressor are under the gate structure.

2. The method of claim 1, wherein the first stressor is formed of one material selected from the group consisting of He, Ne, and Ga implanted into the substrate.

3. The method of claim 1, wherein the ion beam is a focused ion beam.

4. The method of claim 1, wherein no implantation hardmask is used to form the first stressor.

5. The method of claim 1, further comprising performing an annealing process after forming the first stressor.

6. The method of claim 1, wherein the first stressor is formed in a region under the gate structure that is adjacent to a region that is under a central region of the semiconductor fin.

7. The method of claim 1, wherein the substrate is one selected from the group consisting of a Si substrate, a Ge substrate, a SiGe substrate, a GaAs substrate, and an InGaAs substrate.

8. The method of claim 1, wherein a concentration of a material in the first stressor is from about 10¹⁰/cm³ to about 10²⁰/cm³.

9. The method of claim 1, wherein a concentration of a material in the first stressor is from about 10¹⁵/cm³ to about 10²⁰/cm³.

13. The method of claim 1, wherein the second stressor is formed after forming the first stressor.

14. The method of claim 1, wherein the gate insulating layer and the gate electrode layer are formed after forming the first stressor.

15. The method of claim 1, wherein a lattice constant of the first stressor is greater than that of a region of the substrate immediately adjacent to the first stressor.

10. A method for forming a nanowire on a semiconductor substrate, the method comprising:

forming a mask layer on the semiconductor substrate;

applying ion current on a region of the mask layer, such that ions of the ion current bombard the region of the mask layer to form an opening in the mask layer, wherein the ions settle in a region in the semiconductor substrate so as to form a stressor; and

growing the nanowire on a portion of the substrate exposed by the opening of the mask layer.

11. The method of claim 10, wherein the ions are one selected from the group consisting of He, Ne, and Ga.

12. The method of claim 10, wherein the substrate is a silicon substrate, the mask layer is a silicon oxide layer, and the nanowire is an InAs nanowire perpendicularly grown on the silicon substrate.

16. A method for manufacturing a semiconductor device including a first transistor and a second transistor, the method comprising:

sequentially forming first and second stressors in a substrate;

forming a first gate insulating layer and a first gate electrode for the first transistor over the first stressor, and a second gate insulating layer and a second gate electrode for the second transistor over the second stressor; and

forming a first source region and a first drain region for the first transistor on opposite sides of the first gate insulating layer and the first gate electrode, and a second source region and a second drain region for the second transistor on opposite sides of the second gate insulating layer and the second gate electrode,

wherein the first transistor and the second transistor are N-type transistors, or the first transistor and the second transistor are P-type transistors.

17. The method of claim 16, wherein the first and second stressors are formed of one material selected from the group consisting of He, Ne, and Ga implanted into the substrate.

18. The method of claim 16, wherein the first and second stressors are sequentially formed by a focused ion beam without using an ion implantation mask.

19. The method of claim 16, further comprising performing an annealing process after forming the first and second stressors.

20. The method of claim 16, wherein the substrate is one selected from the group consisting of a Si substrate, a Ge substrate, a SiGe substrate, a GaAs substrate, an InGaAs substrate, and a silicon-on-insulator substrate.