Semiconductor device and manufacturing method thereof

• US 10,516,055 B2
• Filed: 03/13/2018
• Issued: 12/24/2019
• Est. Priority Date: 11/13/2009
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Yamazaki, Shunpei, Koyama, Jun
• Primary Examiner(s): Cao, Phat X
• Application Number:
  US15/919,437
• Publication Number:
  US 20180269330A1
• Time in Patent Office: 651 Days
• CPC Class Codes: H01L 29/045 by their particular orientation of crystalline planes
• CPC Class Codes: H01L 29/24 including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22 including organic materials H10K99/00
• CPC Class Codes: H01L 29/45 Ohmic electrodes
• CPC Class Codes: H01L 29/66757 Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
• CPC Class Codes: H01L 29/66969 of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/78618 characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure silicide contacts, electrodes in general H01L29/458
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

A semiconductor device includes an oxide semiconductor layer, a source electrode and a drain electrode electrically connected to the oxide semiconductor layer, a gate insulating layer covering the oxide semiconductor layer, the source electrode, and the drain electrode, and a gate electrode over the gate insulating layer. The source electrode and the drain electrode include an oxide region formed by oxidizing a side surface thereof. Note that the oxide region of the source electrode and the drain electrode is preferably formed by plasma treatment with a high frequency power of 300 MHz to 300 GHz and a mixed gas of oxygen and argon.

Claims

1. A method for manufacturing a semiconductor device comprising:

a first step of forming an oxide semiconductor layer comprising In, Ga and Zn;

a second step of performing a first heat treatment at a temperature of higher than or equal to 400°

C. and lower than or equal to 700°

C. after the first step;

a third step of forming a source electrode and a drain electrode each overlapping with the oxide semiconductor layer after the second step;

a fourth step of performing a plasma treatment in an atmosphere containing oxygen after the third step;

a fifth step of forming a first insulating layer over the source electrode and the drain electrode after the fourth step;

a sixth step of performing a second heat treatment after the fifth step; and

a seventh step of forming a second insulating layer over the first insulating layer after the sixth step,

wherein the first insulating layer is in contact with the oxide semiconductor layer,

wherein the first insulating layer comprising silicon oxide,

wherein the second insulating layer comprising silicon nitride,

wherein each of the source electrode and the drain electrode comprise copper, and

wherein a side surface of the source electrode and a side surface of the drain electrode each comprise an oxidized region.

2. The method for manufacturing a semiconductor device according to claim 1,

wherein a side surface of the oxide semiconductor layer is in contact with the source electrode and the drain electrode.

3. The method for manufacturing a semiconductor device according to claim 1, further comprising:

an eighth step of forming a gate electrode,

wherein the oxide semiconductor layer and the gate electrode overlaps with each other.

4. The method for manufacturing a semiconductor device according to claim 1,

wherein the oxide semiconductor layer after the first step comprises a crystal.

5. The method for manufacturing a semiconductor device according to claim 4,

wherein c-axis of the crystal is perpendicular to a surface of the oxide semiconductor layer.

6. A method for manufacturing a semiconductor device comprising:

a first step of forming an oxide semiconductor layer comprising In, Ga and Zn;

a second step of performing a first heat treatment at a temperature of higher than or equal to 400°

C. and lower than or equal to 700°

C. after the first step;

a third step of forming a source electrode and a drain electrode each overlapping with the oxide semiconductor layer after the second step;

a fourth step of performing a plasma treatment in an atmosphere containing oxygen after the third step;

a fifth step of forming a first insulating layer over the source electrode and the drain electrode after the fourth step;

a sixth step of performing a second heat treatment at a temperature of higher than or equal to 200°

C. and lower than or equal to 400°

C. after the fifth step; and

a seventh step of forming a second insulating layer over the first insulating layer after the sixth step,

wherein the first insulating layer is in contact with the oxide semiconductor layer,

wherein the first insulating layer comprising silicon oxide,

wherein the second insulating layer comprising silicon nitride,

wherein each of the source electrode and the drain electrode comprise copper, and

wherein a side surface of the source electrode and a side surface of the drain electrode each comprise an oxidized region.

7. The method for manufacturing a semiconductor device according to claim 6,

wherein a side surface of the oxide semiconductor layer is in contact with the source electrode and the drain electrode.

8. The method for manufacturing a semiconductor device according to claim 6, further comprising:

an eighth step of forming a gate electrode,

wherein the oxide semiconductor layer and the gate electrode overlaps with each other.

9. The method for manufacturing a semiconductor device according to claim 6,

wherein the oxide semiconductor layer after the first step comprises a crystal.

10. The method for manufacturing a semiconductor device according to claim 9,

wherein c-axis of the crystal is perpendicular to a surface of the oxide semiconductor layer.

11. A method for manufacturing a semiconductor device comprising:

a first step of forming an oxide semiconductor layer comprising In, Ga and Zn;

a second step of performing a first heat treatment at a temperature of higher than or equal to 400°

C. and lower than or equal to 700°

C. after the first step;

a third step of forming a source electrode and a drain electrode each overlapping with the oxide semiconductor layer after the second step;

a fourth step of performing a plasma treatment in an atmosphere containing oxygen after the third step;

a fifth step of forming a first insulating layer over the source electrode and the drain electrode after the fourth step;

a sixth step of performing a second heat treatment after the fifth step; and

a seventh step of forming a second insulating layer over the first insulating layer after the sixth step,

wherein the first insulating layer is in contact with the oxide semiconductor layer,

wherein the first insulating layer comprising silicon oxide,

wherein the second insulating layer comprising silicon nitride,

wherein each of the source electrode and the drain electrode comprise copper, and

wherein a side surface of the source electrode and a side surface of the drain electrode each comprise an oxidized region having a thickness of 5 nm or more.

12. The method for manufacturing a semiconductor device according to claim 11,

wherein a side surface of the oxide semiconductor layer is in contact with the source electrode and the drain electrode.

13. The method for manufacturing a semiconductor device according to claim 11, further comprising:

an eighth step of forming a gate electrode,

wherein the oxide semiconductor layer and the gate electrode overlaps with each other.

14. The method for manufacturing a semiconductor device according to claim 11,

wherein the oxide semiconductor layer after the first step comprises a crystal.

15. The method for manufacturing a semiconductor device according to claim 14,

wherein c-axis of the crystal is perpendicular to a surface of the oxide semiconductor layer.