Predistorter for compensating linearity of an amplifier

• US 10,516,370 B2
• Filed: 06/26/2019
• Issued: 12/24/2019
• Est. Priority Date: 02/15/2017
• Status: Active Grant

• Current Assignee: RichWave Technology Corp
• Original Assignee: RichWave Technology Corp
• Inventors: Chen, Chih-Sheng, Hsieh, Pei-Chuan
• Primary Examiner(s): Nguyen, Patricia T
• Application Number:
  US16/452,549
• Publication Number:
  US 20190319590A1
• Time in Patent Office: 181 Days
• CPC Class Codes: H03F 1/0205 in transistor amplifiers
• CPC Class Codes: H03F 1/0261 with control of the polarisation voltage or current, e.g. gliding Class A
• CPC Class Codes: H03F 1/3241 using predistortion circuits H03F1/3211, H03F1/3217 take precedence
• CPC Class Codes: H03F 1/3276 using the nonlinearity inherent to components, e.g. a diode
• CPC Class Codes: H03F 2200/18 the bias of the gate of a FET being controlled by a control signal
• CPC Class Codes: H03F 2200/451 the amplifier being a radio frequency amplifier
• CPC Class Codes: H03F 3/19 with semiconductor devices only
• CPC Class Codes: H03F 3/21 with semiconductor devices only H03F3/245 takes precedence

Abstract

A predistorter has a first capacitor, a first bias input circuit, a second bias input circuit, a second capacitor and an impedance conversion circuit. A first end of the first capacitor is coupled to a first node of the amplifier. The impedance conversion circuit has a first resistor and a field-effect transistor (FET) and is used to perform an impedance conversion to provide a variable capacitance. A gate of the FET is coupled to an output end of the first bias input circuit, one of a source and a drain of the FET is coupled to a second end of the first capacitor and a first end of the first resistor, and another of the source and the drain of the FET is coupled to an output end of the second bias input circuit, first end of the second capacitor and a second end of the first resistor.

Claims

1. A predistorter for compensating linearity of an amplifier, the predistorter comprising:

a first capacitor having a first end coupled to a first node of the amplifier;

a first bias input circuit configured to receive a first bias;

a second bias input circuit configured to receive a second bias;

a second capacitor; and

an impedance conversion circuit configured to perform an impedance conversion to provide a variable capacitance, the impedance conversion circuit comprising;

a first resistor; and

a field-effect transistor (FET);

wherein a gate of the FET is coupled to an output end of the first bias input circuit, one of a source and a drain of the FET is coupled to a second end of the first capacitor and a first end of the first resistor, another of the source and the drain of the FET is coupled to an output end of the second bias input circuit, a first end of the second capacitor and a second end of the first resistor, and a second end of the second capacitor is coupled to a second node of the amplifier.

2. The predistorter of claim 1, wherein the first node is an input end of the amplifier, and the second node is coupled to a reference voltage.

3. The predistorter of claim 1, wherein the first node is an end of a bias circuit of the amplifier, and the second node is coupled to a reference voltage.

4. The predistorter of claim 1, wherein the first node is coupled to an output end of a first order circuit of the amplifier, and the second node is coupled to an input end of a second order circuit of the amplifier.

5. The predistorter of claim 1, wherein one of the first bias and the second bias is a constant voltage, and another of the first bias and the second bias is varied with an input power of the amplifier.

6. The predistorter of claim 1 further comprising a selection circuit configured to select the first bias from a first voltage and a second voltage, wherein the first voltage is a constant voltage, and the second voltage is varied with an input power of the amplifier.

7. The predistorter of claim 6, wherein the selection circuit comprises:

a first input end configured to receive the first voltage;

a second input end configured to receive the second voltage; and

a first output end, coupled to an input end of the first bias input circuit to provide the first bias;

a second output end, coupled to an input end of the second bias input circuit to provide the second bias; and

a control end configured to receive a selection control signal;

wherein when the selection control signal is at a first voltage level, the selection circuit couples the first input end to the first output end and couples the second input end to the second output end; and

wherein when the selection control signal is at a second voltage level, the selection circuit couples the first input end to the second output end and couples the second input end to the first output end.

8. The predistorter of claim 6 further comprising a dynamic bias adjusting circuit coupled to an input end of the amplifier and configured to dynamically adjust the second voltage according to the input power of the amplifier.

9. The predistorter of claim 8, wherein the dynamic bias adjusting circuit comprises:

a first resistor-capacitor circuit having an input end coupled to the input end of the amplifier;

a transistor having a first end coupled to a system voltage, and a control end coupled to an output end of the first resistor-capacitor circuit;

a second resistor-capacitor circuit, coupled between a reference voltage and a second end of the transistor; and

an operational amplifier having a first input end coupled to the second end of the transistor, a second input end, and an output end coupled to the second end of the operational amplifier and configured to output the second voltage.

10. The predistorter of claim 1, wherein the first bias input circuit comprises a second resistor, and the second bias input circuit comprises a third resistor;

wherein a first end of the second resistor receives the first bias, and a second end of the second resistor is coupled to the output end of the first bias input circuit; and

wherein a first end of the third resistor receives the second bias, and a second end of the third resistor is coupled to the output end of the second bias input circuit.