Method and apparatus to shutdown a memory channel

• US 10,521,003 B2
• Filed: 04/03/2017
• Issued: 12/31/2019
• Est. Priority Date: 12/22/2011
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Nachimuthu, Murugasamy K., Kumar, Mohan J.
• Primary Examiner(s): Prifti, Aurel
• Application Number:
  US15/477,857
• Publication Number:
  US 20170206010A1
• Time in Patent Office: 1,002 Days
• Field of Search: 711154, 711103, 711170, 711207, 713320, 713323, 713324, 370412, 37039552, 710301
• CPC Class Codes: G06F 1/3275 Power saving in memory, e.g. RAM, cache
• CPC Class Codes: G06F 12/08 in hierarchically structured memory systems, e.g. virtual memory systems
• CPC Class Codes: G06F 12/0802 Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
• CPC Class Codes: G06F 12/0804 with main memory updating G06F12/0806 takes precedence
• CPC Class Codes: G06F 12/0888 using selective caching, e.g. bypass
• CPC Class Codes: G06F 12/1027 using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
• CPC Class Codes: G06F 2212/1028 Power efficiency
• CPC Class Codes: G06F 2212/1044 Space efficiency improvement
• CPC Class Codes: G06F 2212/2024 Rewritable memory not requiring erasing, e.g. resistive or ferroelectric RAM
• CPC Class Codes: G06F 2212/205 Hybrid memory, e.g. using both volatile and non-volatile memory
• CPC Class Codes: G06F 2212/60 Details of cache memory
• CPC Class Codes: G06F 3/061 Improving I/O performance
• CPC Class Codes: G06F 3/0625 Power saving in storage systems
• CPC Class Codes: G06F 3/0647 Migration mechanisms
• CPC Class Codes: G06F 3/0685 Hybrid storage combining heterogeneous device types, e.g. hierarchical storage, hybrid arrays
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A method is described that includes deciding to enter a lower power state, and, shutting down a memory channel in a computer system in response where thereafter other memory channels in the computer system remain active so that computer remains operative while the memory channel is shutdown.

Claims

1. A method, comprising:

deciding to enter a lower power state; and

,

shutting down a memory channel in a computer system in response where thereafter other memory channels in said computer system remain active so that said computer system remains operative while said memory channel is shutdown, wherein the shutting down of the memory channel comprises migrating a first unit of data from the memory channel to a volatile memory device that is coupled to a first active memory channel, and, migrating a second unit of data from the memory channel to a non volatile memory device that is coupled to a second active memory channel, where, the first unit of data has a history of greater usage than the second unit of data, and wherein the second active memory channel is allocated system memory address space.

2. The method of claim 1 wherein said method further comprises

changing a power node structure of a memory power state table to shutdown said memory channel, where, said power node structure represents said memory channel.

3. The method of claim 2 wherein said power node structure identifies a range of virtual addresses whose corresponding cache lines are stored on said memory channel.

4. The method of claim 3 wherein multiple instances of said power node structure are created to represent said memory channel, each unique instance having a different set of virtual addresses whose corresponding cache lines are stored in said memory channel.

5. The method of claim 2 wherein said power node structure has a field to represent said memory channel'"'"'s current power state.

6. The method of claim 2 wherein said memory power state table includes multiple power node structures to represent multiple respective memory channels.

7. The method of claim 6 wherein said memory power stable includes characteristics of the different power states of said multiple respective memory channels.

8. A machine readable storage medium, and not transitory propagating signals, containing program code that when processed by a central processing unit of a computing system causes a method to be performed, said method comprising:

deciding to enter a lower power state; and

,

changing a power node structure of a memory power state table to shutdown a memory channel in a computer system;

as part of the shutdown of the memory channel performing the following;

recognizing that the first data unit has a usage history that is greater than a second data unit;

migrating the first data unit from the memory channel to a volatile memory device that is coupled to a first active memory channel;

migrating the second data unit from the memory channel to a non volatile memory device that is coupled to a second active memory channel, wherein the second active memory is allocated system memory address space.

9. The machine readable storage medium of claim 8 wherein said power node structure represents said memory channel.

10. The machine readable storage medium of claim 9 wherein said power node structure identifies a range of virtual addresses whose corresponding cache lines are stored on said memory channel.

11. The machine readable storage medium of claim 10 wherein multiple instances of said power node structure are created to represent said memory channel, each unique instance having a different set of virtual addresses whose corresponding cache lines are stored in said memory channel.