Memory device including mixed non-volatile memory cell types

• US 10,521,130 B2
• Filed: 11/20/2018
• Issued: 12/31/2019
• Est. Priority Date: 01/18/2017
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Tanzawa, Toru
• Primary Examiner(s): Yang, Han
• Application Number:
  US16/197,208
• Publication Number:
  US 20190087103A1
• Time in Patent Office: 406 Days
• Field of Search: 36518511, 36518513
• CPC Class Codes: G06F 3/0613 in relation to throughput
• CPC Class Codes: G06F 3/0625 Power saving in storage systems
• CPC Class Codes: G06F 3/064 Management of blocks
• CPC Class Codes: G06F 3/0656 Data buffering arrangements
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G11C 11/005 comprising combined but independently operative RAM-ROM, RAM-PROM, RAM-EPROM cells
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 11/5635 Erasing circuits
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 11/5657 using ferroelectric storage elements
• CPC Class Codes: G11C 11/5671 using charge trapping in an insulator
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/3459 Circuits or methods to verify correct programming of nonvolatile memory cells
• CPC Class Codes: H01L 29/516 with at least one ferroelectric layer
• CPC Class Codes: H10B 41/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 41/35 with a cell select transistor, e.g. NAND
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/35 with cell select transistors, e.g. NAND
• CPC Class Codes: H10B 51/20 characterised by the three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 51/30 characterised by the memory core region

Abstract

Some embodiments include apparatuses, and methods of forming and operating the apparatuses. Some of the apparatuses include a conductive line, non-volatile memory cells of a first memory cell type, the non-volatile memory cells coupled in series among each other, and an additional non-volatile memory cell of a second memory cell type coupled to the conductive line and coupled in series with the non-volatile memory cells of the first memory cell type. The second memory cell type is different from the first memory cell type.

Claims

1. An apparatus comprising:

a data line;

a first plurality of sub-blocks coupled to the data line, each sub-block of the first plurality of sub-blocks including memory cell strings;

a second plurality of sub-blocks coupled to the data line, each sub-block of the second plurality of sub-blocks including memory cell strings;

a buffer circuit to receive first information; and

a control unit to store second information in the first plurality of sub-blocks and to store third information in the second plurality of sub-blocks, wherein a value of the second information is based on a value of the first information received at the buffer circuit, and a value of the third information is based on the value of the second information.

2. The apparatus of claim 1, wherein each sub-block of each of the first and second pluralities of sub-blocks includes memory cells having different memory cell types.

3. The apparatus of claim 1, wherein the first plurality of sub-blocks includes memory cells having a first memory cell type, the second plurality of sub-blocks includes memory cells having a second memory cell type different from the first memory cell type, and the control unit is configured to store the second information in the memory cells having the first memory cell type, and to store the third information in the memory cells having the second memory cell type.

4. The apparatus of claim 1, wherein the first plurality of sub-blocks includes pillars associated with the memory cell strings of the first plurality of sub-blocks, and the control unit is configured to store the second information having a value based on potentials of the pillars.

5. The apparatus of claim 1, wherein the second plurality of sub-blocks includes:

a first sub-block and a second sub-block;

a first select gate coupled between the data line and the first sub-block; and

a second select gate coupled between the data line and the second sub-block, and the control unit is configured to concurrently activate the first and second select gates during an operation of storing the third information in the second plurality of sub-blocks.

6. The apparatus of claim 1, further comprising first access lines and second access lines separated from the first access lines, wherein the first plurality of sub-blocks shares the first access lines, and the second plurality of sub-blocks shares the second access lines.

7. The apparatus of claim 1, wherein each sub-block of each of the first and second pluralities of sub-blocks includes:

first memory cells having a first memory cell type; and

a second memory cell having a second memory cell type, and each of the first memory cells is configured to store more bits of information than the second memory cell.

8. The apparatus of claim 7, wherein each of the first memory cells includes a charge storage structure configured to store information, and the charge storage structure is polysilicon.

9. The apparatus of claim 7, wherein each of the first memory cells includes a charge storage structure configured to store information, and the charge storage structure is silicon nitride.

10. The apparatus of claim 7, wherein the second memory cell includes a ferroelectric material.

11. An apparatus comprising:

a conductive line;

a first memory cell block including first sub-blocks coupled to the conductive line, each of the first sub-blocks including a first memory cell string and a first additional memory cell, the first memory cell string including first memory cells coupled in series with the first additional memory cell;

a second memory cell block including second sub-blocks coupled to the conductive line, each of the second sub-blocks including a second memory cell string and a second additional memory cell, the second memory cell string including second memory cells coupled in series with the second additional memory cell, wherein the first memory cells and the second memory cells have a first memory cell type, and the first and second additional memory cells have a second memory type;

first access lines coupled to the first memory block; and

second access lines coupled to the second memory cell block, the second access lines being separated from the first access lines.

12. The apparatus of claim 11, further comprising an additional conductive line coupled to each of the first sub-blocks and each of the second sub-blocks, wherein:

each of the first sub-blocks and each of the second sub-blocks includes a memory cell string and an additional memory cell;

the memory cell string includes memory cells coupled in series with the additional memory cell; and

the memory cells have the first memory cell type, and the additional memory cell has the second memory type.

13. The apparatus of claim 12, wherein:

the memory cell string of the first sub-blocks shares the first access lines with the first memory cell string of the first sub-blocks; and

the memory cell string of the second sub-blocks shares the second access lines with the second memory cell string of the second sub-blocks.

14. The apparatus of claim 13, further comprising:

a first select gate coupled between the first additional memory cell and the first memory cell string of the first sub-blocks;

a second select gate coupled between the second additional memory cell and the second memory cell string of the second sub-blocks;

a third select gate coupled between the additional memory cell of the first sub-blocks and the memory cell string of the first sub-blocks;

a fourth select gate coupled between the additional memory cell of the second sub-blocks and the memory cell string of the second sub-blocks.

15. The apparatus of claim 13, further comprising:

a first additional select gate coupled between the first memory cell string of the first sub-block and a source;

a second additional select gate coupled between the second memory cell string of the second sub-blocks and the source;

a third additional select gate coupled between the memory cell string of the first sub-blocks and the source;

a fourth additional select gate coupled between the memory cell string of the second sub-blocks and the source.

16. A method comprising:

receiving first information;

storing the first information in a first portion of a memory device, the first portion of the memory device including a first plurality of memory cells coupled to a data line, the first plurality of memory cells having a first non-volatile memory cell type; and

storing second information in a second portion the memory device after the first information is stored in the first portion of the memory device, the second information having a value based on a value of the first information stored in the first portion of the memory device, the second portion of the memory device including a second plurality of memory cells coupled to the data line, and the second plurality of memory cells having a second non-volatile memory cell type different from the first non-volatile memory cell type.

17. The method of claim 16, wherein storing the second information includes:

changing a threshold voltage of a memory cell of the second plurality of memory cells; and

determining whether the threshold voltage of the memory cell reaches a target threshold voltage based on the value of the first information stored in the first portion of the memory device.

18. The method of claim 16, wherein storing the first information includes:

storing in a first memory cell of the first plurality of memory cells only one bit among a plurality of bits included in the first information; and

storing in a second memory cell of the first plurality of memory cells only one bit among the plurality of bits included in the first information.

19. The method of claim 16, wherein storing the first information includes:

changing the potential of a pillar associated with a portion of the first plurality of memory cells, such that a value of a bit of the first information is based on a value of the potential of the pillar.

20. The method of claim 16, wherein storing the second information includes:

storing in a first memory cell of the second plurality of memory cells first multiple bits among a plurality of bits included in the second information; and

storing in a second memory cell of the second plurality of memory cells second multiple bits among the plurality of bits included in the second information.