Unified extensible firmware interface updates

• US 10,521,216 B2
• Filed: 01/17/2017
• Issued: 12/31/2019
• Est. Priority Date: 01/17/2017
• Status: Active Grant

• Current Assignee: Oracle International Corporation (Oracle Corporation)
• Original Assignee: Oracle International Corporation (Oracle Corporation)
• Inventors: Yu, Yadong
• Primary Examiner(s): Sough, S.
• Assistant Examiner(s): Wei, Zengpu
• Application Number:
  US15/408,033
• Publication Number:
  US 20180203682A1
• Time in Patent Office: 1,078 Days
• Field of Search: 717168
• CPC Class Codes: G06F 8/65 Updates security arrangements therefor G06F21/57
• CPC Class Codes: G06F 9/4405 Initialisation of multiprocessor systems
• CPC Class Codes: G06F 9/4406 Loading of operating system
• CPC Class Codes: G06F 9/4411 Configuring for operating with peripheral devices; Loading of device drivers

Abstract

A method of executing processor-specific code to include board-specific optimizations in a Unified Extensible Firmware Interface (UEFI) may include executing first instructions that are specific to a processor, where the first instructions may be executed within a UEFI firmware routine. The method may also include detecting a portion of the first instructions that requires information to be processed or provided by second instructions, where the second instructions may be specific to a circuit board on which the processor is installed. The method may further include sending, through an intermediate dispatch function, a request for the information to be processed or provided by the second instructions, where the intermediate dispatch function can decouple the first instructions from the second instructions.

Claims

1. A method of executing processor-specific code to include board-specific optimizations in a Unified Extensible Firmware Interface (UEFI), the method comprising:

executing first instructions in a reference code module, wherein the first instructions in the reference code module are part of a UEFI firmware routine and specific to a current processor;

detecting a portion of the first instructions that requires information to be processed or provided by second instructions within the UEFI, wherein the second instructions are part of a circuit board module that is specific to a circuit board on which the processor is installed;

sending, through an intermediate dispatch function, a request from the reference code module to the circuit board module for the information to be processed or provided by the second instructions, wherein the intermediate dispatch function decouples the reference code module from the circuit board module, and wherein the request comprises a reference to an execution context of the first instructions that requires board-specific processing; and

receiving, through the intermediate dispatch function, results from the second instructions, wherein the intermediate dispatch function receives a void pointer from the second instructions that references the results of the second instructions, and the intermediate dispatch function casts the void pointer into a datatype required by the first instructions.

2. The method of claim 1, further comprising:

continuing execution of the first instructions.

3. The method of claim 1, further comprising:

receiving, through the intermediate dispatch function, an indication that the second instructions have successfully executed; and

continuing execution of the first instructions.

4. The method of claim 1, wherein the reference code module was received from a manufacturer of the processor.

5. The method of claim 1, wherein the circuit board module was received by a manufacturer of the circuit board.

6. The method of claim 1, wherein the intermediate dispatch function does not require any static links between the first instructions and the second instructions.

7. The method of claim 1, wherein the information to be processed or provided by the second instructions comprises a set of initialization parameters.

8. The method of claim 1, wherein the execution context of the first instructions comprises chipset devices and subcomponent topology data that require a board-specific initialization.

9. The method of claim 1, wherein the execution context of the first instructions comprises chipset configuration policy tokens that require a board-specific override.

10. The method of claim 1, wherein the execution context of the first instructions comprises chipset initialization health data that requires board-specific processing.

11. The method of claim 1, further comprising:

casting, by the intermediate dispatch function, the execution context of the first instructions into a void pointer, such that the second instructions are not required to use data structures that are specific to the first instructions.

12. The method of claim 1, further comprising:

generating, at the intermediate dispatch function, a unique ID for the request.

13. The method of claim 12, further comprising:

passing the unique ID to the second instructions as a function parameter in a call stack.

14. The method of claim 12, further comprising:

generating, at the intermediate dispatch function, a plurality of unique IDs from the unique ID that are assigned to forked processes executed by the second instructions.

15. The method of claim 14, wherein each of the plurality of unique IDs target specific board-specific customization functions.

16. The method of claim 1, wherein the processor comprises a CPU or chipset.

17. A non-transitory, computer-readable medium comprising instructions that, when executed by one or more processors, causes the one or more processors to perform operations comprising:

executing first instructions in a reference code module, wherein the first instructions in the reference code module are part of a UEFI firmware routine and specific to a current processor;

detecting a portion of the first instructions that requires information to be processed or provided by second instructions within the UEFI, wherein the second instructions are part of a circuit board module that is specific to a circuit board on which the processor is installed;

sending, through an intermediate dispatch function, a request from the reference code module to the circuit board module for the information to be processed or provided by the second instructions, wherein the intermediate dispatch function decouples the reference code module from the circuit board module, and wherein the request comprises a reference to an execution context of the first instructions that requires board-specific processing; and

receiving, through the intermediate dispatch function, results from the second instructions, wherein the intermediate dispatch function receives a void pointer from the second instructions that references the results of the second instructions, and the intermediate dispatch function casts the void pointer into a datatype required by the first instructions.

18. The non-transitory computer-readable medium according to claim 17 wherein the execution context of the first instructions comprises chipset devices and subcomponent topology data that require a board-specific initialization.

19. The non-transitory computer-readable medium according to claim 17 wherein the execution context of the first instructions comprises chipset configuration policy tokens that require a board-specific override.

20. The non-transitory computer-readable medium according to claim 17 wherein the execution context of the first instructions comprises chipset initialization health data that requires board-specific processing.

21. The non-transitory computer-readable medium according to claim 17 comprising additional instruction that cause the one or more processors to perform additional operations comprising:

casting, by the intermediate dispatch function, the execution context of the first instructions into a void pointer, such that the second instructions are not required to use data structures that are specific to the first instructions.

22. The non-transitory computer-readable medium according to claim 17, comprising additional instruction that cause the one or more processors to perform additional operations comprising:

continuing execution of the first instructions.

23. The non-transitory computer-readable medium according to claim 17, comprising additional instruction that cause the one or more processors to perform additional operations comprising:

receiving, through the intermediate dispatch function, an indication that the second instructions have successfully executed; and

continuing execution of the first instructions.

24. The non-transitory computer-readable medium according to claim 17, wherein the reference code module was received from a manufacturer of the processor.

25. The non-transitory computer-readable medium according to claim 17, wherein the circuit board module was received by a manufacturer of the circuit board.

26. The non-transitory computer-readable medium according to claim 17, wherein the intermediate dispatch function does not require any static links between the first instructions and the second instructions.

27. The non-transitory computer-readable medium according to claim 17, wherein the information to be processed or provided by the second instructions comprises a set of initialization parameters.

28. The non-transitory computer-readable medium according to claim 17, comprising additional instruction that cause the one or more processors to perform additional operations comprising:

generating, at the intermediate dispatch function, a unique ID for the request.

29. The non-transitory computer-readable medium according to claim 28, comprising additional instruction that cause the one or more processors to perform additional operations comprising:

passing the unique ID to the second instructions as a function parameter in a call stack.

30. The non-transitory computer-readable medium according to claim 28, comprising additional instruction that cause the one or more processors to perform additional operations comprising:

generating, at the intermediate dispatch function, a plurality of unique IDs from the unique ID that are assigned to forked processes executed by the second instructions.

31. The non-transitory computer-readable medium according to claim 30, wherein each of the plurality of unique IDs target specific board-specific customization functions.

32. The non-transitory computer-readable medium according to claim 17, wherein the processor comprises a CPU or chipset.

33. A system comprising:

one or more processors; and

one or more memory devices comprising instructions that, when executed by the one or more processors, cause the one or more processors to perform operations comprising;

executing first instructions in a reference code module, wherein the first instructions in the reference code module are part of a UEFI firmware routine and specific to a current processor;

detecting a portion of the first instructions that requires information to be processed or provided by second instructions within the UEFI, wherein the second instructions are part of a circuit board module that is specific to a circuit board on which the processor is installed;

sending, through an intermediate dispatch function, a request from the reference code module to the circuit board module for the information to be processed or provided by the second instructions, wherein the intermediate dispatch function decouples the reference code module from the circuit board module, and wherein the request comprises a reference to an execution context of the first instructions that requires board-specific processing; and

receiving, through the intermediate dispatch function, results from the second instructions, wherein the intermediate dispatch function receives a void pointer from the second instructions that references the results of the second instructions, and the intermediate dispatch function casts the void pointer into a datatype required by the first instructions.

34. The system of claim 33, wherein the one or more memory devices further comprise additional instructions that cause the one or more processors to perform additional operations comprising:

generating, at the intermediate dispatch function, a unique ID for the request.

35. The system of claim 34, wherein the one or more memory devices further comprise additional instructions that cause the one or more processors to perform additional operations comprising:

passing the unique ID to the second instructions as a function parameter in a call stack.

36. The system of claim 34, wherein the one or more memory devices further comprise additional instructions that cause the one or more processors to perform additional operations comprising:

generating, at the intermediate dispatch function, a plurality of unique IDs from the unique ID that are assigned to forked processes executed by the second instructions.

37. The system of claim 36, wherein each of the plurality of unique IDs target specific board-specific customization functions.

38. The system of claim 33, wherein the processor comprises a CPU or chipset.

39. The system of claim 33, wherein the one or more memory devices further comprise additional instructions that cause the one or more processors to perform additional operations comprising:

continuing execution of the first instructions.

40. The system of claim 33, wherein the one or more memory devices further comprise additional instructions that cause the one or more processors to perform additional operations comprising:

receiving, through the intermediate dispatch function, an indication that the second instructions have successfully executed; and

continuing execution of the first instructions.

41. The system of claim 33, wherein the reference code module was received from a manufacturer of the processor.

42. The system of claim 33, wherein the circuit board module was received by a manufacturer of the circuit board.

43. The system of claim 33, wherein the intermediate dispatch function does not require any static links between the first instructions and the second instructions.

44. The system of claim 33, wherein the information to be processed or provided by the second instructions comprises a set of initialization parameters.

45. The system of claim 33, wherein the execution context of the first instructions comprises chipset devices and subcomponent topology data that require a board-specific initialization.

46. The system of claim 33, wherein the execution context of the first instructions comprises chipset configuration policy tokens that require a board-specific override.

47. The system of claim 33, wherein the execution context of the first instructions comprises chipset initialization health data that requires board-specific processing.

48. The system of claim 33, wherein the one or more memory devices further comprise additional instructions that cause the one or more processors to perform additional operations comprising:

casting, by the intermediate dispatch function, the execution context of the first instructions into a void pointer, such that the second instructions are not required to use data structures that are specific to the first instructions.