System and method for individual addressing

• US 10,521,366 B2
• Filed: 05/01/2019
• Issued: 12/31/2019
• Est. Priority Date: 09/29/2016
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Bell, Debra, Glendenning, Paul, Brown, David R., Noyes, Harold B
• Primary Examiner(s): Tseng, Cheng Yuan
• Application Number:
  US16/400,739
• Publication Number:
  US 20190258592A1
• Time in Patent Office: 244 Days
• Field of Search: None
• CPC Class Codes: G06F 13/126 and has means for transferring I/O instructions and statuses between control unit and main processor
• CPC Class Codes: G06F 13/287 Multiplexed DMA G06F13/30 takes precedence
• CPC Class Codes: G06F 13/4022 using switching circuits, e.g. switching matrix, connection or expansion network G06F13/4009 takes precedence
• CPC Class Codes: G06F 13/404 with address mapping
• CPC Class Codes: G06F 2213/2802 DMA using DMA transfer descriptors

Abstract

In one embodiment, a system includes a bus interface including a first processor, an indirect address storage storing a number of indirect addresses, and a direct address storage storing a number of direct addresses. The system also includes a number of devices connected to the bus interface and configured to analyze data. Each device of the number of devices includes a state machine engine. The bus interface is configured to receive a command from a second processor and to transmit an address for loading into the state machine engine of at least one device of the number of devices. The address includes a first address from the number of indirect addresses or a second address from the number of direct addresses.

Claims

1. A device comprising:

a bus interface; and

a plurality of state machine engines connected to the bus interface in a rank, wherein each of the plurality of state machine engines comprises a plurality of configurable elements, each configurable element of the plurality of configurable elements comprising a data analysis element comprising a memory component programmed with configuration data to selectively set a data state of the memory component as one of a high state and a low state, wherein the data analysis element is configured to analyze at least a portion of a data stream based on the data state of the memory component and to output a result of the analysis, wherein each of the plurality of state machine engines is configured to receive a respective address of a plurality of addresses from the bus interface for loading prior to executing a command from a processor or an instruction buffer.

2. The device of claim 1, wherein each respective address of the plurality of addresses comprises a direct address, an indirect address, or a dummy address.

3. The device of claim 1, wherein, when at least one respective address of the plurality of addresses comprises an indirect address, the indirect address is automatically incremented by the buffer interface.

4. The device of claim 1, wherein the bus interface comprises a processor, an indirect address storage (IAS), and a multiplexer configured to switch from transmitting the respective address of the plurality of addresses to transmitting an indirect address stored in the IAS when an indirect action is issued by the processor and an enable bit stored in the IAS is set.

5. The device of claim 4, wherein the multiplexer is configured to transmit the respective address of the plurality of addresses comprising a dummy address when the indirect action is issued by the processor and the enable bit stored in the IAS is deselected.

6. The device of claim 1, wherein the bus interface comprises a direct address storage (DAS) and a multiplexer configured to be set to transmit the respective address of the plurality of addresses comprising a direct address stored in the DAS as an output from the DAS.

7. The device of claim 1, wherein a first state machine engine of the plurality of state machine engines is configured to execute the command at a first state machine engine address corresponding to a first address of the plurality of addresses.

8. The device of claim 7, wherein a second state machine engine of the plurality of state machine engines is configured to execute the command at second state machine engine address corresponding to a second address of a plurality of addresses.

9. The device of claim 8, wherein the first state machine engine and the second state machine engine are configured to execute the command in a same bus cycle.

10. A device, comprising:

a state machine engine comprising a plurality of configurable elements, each configurable element of the plurality of configurable elements comprising a data analysis element comprising a memory component programmed with configuration data to selectively set a data state of the memory component as one of a high state and a low state, wherein the data analysis element is configured to analyze at least a portion of a data stream based on the data state of the memory component and to output a result of the analysis, wherein the state machine engine is configured to receive an address from a bus interface, and to load the address, wherein the address comprises a switched output comprising one of either a direct address and an indirect address.

11. The device of claim 10, wherein the address comprising the indirect address is automatically incremented after the indirect address is transmitted by the bus interface.

12. The device of claim 10, wherein the state machine engine is configured to load the address prior to executing a command received by a processor or an instruction buffer.

13. The device of claim 12, wherein the state machine engine is configured execute the command at a first address of the state machine engine when the address comprises a direct address.

14. The device of claim 13, wherein the state machine engine is configured execute the command at a second address of the state machine engine when the address comprises an indirect address.

15. A method, comprising:

receiving a command from a host processor; and

switching from transmission of a first output from a direct address storage (DAS) to a first state machine engine of an electronic device to transmission of a second output from an indirect address storage (IAS) to a second state machine engine of the electronic device based upon the command and an enable indication corresponding to the IAS comprising a first value, wherein each of the first state machine engine and the second state machine engine comprise a plurality of configurable elements, each configurable element of the plurality of configurable elements comprising a data analysis element comprising a memory component programmed with configuration data to selectively set a data state of the memory component as one of a high state and a low state, wherein the data analysis element is configured to analyze at least a portion of a data stream based on the data state of the memory component and to output a result of the analysis.

16. The method of claim 15, comprising switching from transmission of the first output from the DAS to the first state machine engine to ceasing transmission of any output to the first state machine engine and the second state machine engine based upon the command and the enable indication comprising a second value.

17. The method of claim 15, comprising switching from transmission of the first output from the DAS to the first state machine engine to transmission of a third output from the IAS to the second state machine engine of the electronic device based upon the command and the enable indication corresponding to the IAS comprising a second value.

18. The method of claim 17, wherein the second output corresponds to an address of the second state machine engine and the third output corresponds to a dummy address.

19. The method of claim 15, comprising executing a command in the first state machine engine at a first state machine engine address corresponding to the first output and executing the command in the second state machine engine at a second state machine engine address corresponding to the second output.

20. The method of claim 19, comprising executing the command in the first state machine and in the second state machine in a same bus cycle.