Method and structure for mandrel and spacer patterning

• US 10,521,541 B2
• Filed: 04/04/2018
• Issued: 12/31/2019
• Est. Priority Date: 07/16/2015
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Wang, Chung-Ming, Peng, Chih-Hsiung, Chang, Chi-Kang, Chen, Kuei-Shun, Fu, Shih-Chi
• Primary Examiner(s): Aisaka, Bryce M
• Application Number:
  US15/945,356
• Publication Number:
  US 20180225404A1
• Time in Patent Office: 636 Days
• Field of Search: 716119
• CPC Class Codes: G06F 2111/20 Configuration CAD, e.g. designing by assembling or positioning modules selected from libraries of predesigned modules
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36
• CPC Class Codes: H01L 21/823431 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 27/0886 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region

Abstract

A semiconductor device includes a first active fin on a substrate; a second active fin on the substrate and separate from the first active fin; a first fin stub on the substrate, wherein the first fin stub connects a bottom portion of the first active fin and a bottom portion of the second active fin; and an isolation feature over the first fin stub and between the first and second active fins. The first fin stub is lower than both the first and the second active fins in height. The isolation feature is higher than the first fin stub and lower than both the first and the second active fins in height. From a top view, the first active fin is oriented lengthwise in a first direction, and the first fin stub is oriented lengthwise in a second direction that is different from the first direction.

Claims

1. A semiconductor device, comprising:

a first active fin on a substrate;

a second active fin on the substrate and separate from the first active fin;

a first fin stub on the substrate, wherein the first fin stub connects a bottom portion of the first active fin and a bottom portion of the second active fin, wherein the first fin stub is lower than both the first and the second active fins in height; and

an isolation feature over the first fin stub and between the first and second active fins, wherein the isolation feature is higher than the first fin stub and lower than both the first and the second active fins in height, wherein from a top view the first active fin is oriented lengthwise in a first direction, and the first fin stub is oriented lengthwise in a second direction that is different from the first direction.

2. The semiconductor device of claim 1, wherein the first direction and the second direction form an angle not more than 45 degrees.

3. The semiconductor device of claim 1, further comprising:

a third active fin substantially parallel to the first active fin, the first active fin spaced from the third active fin with a first fin pitch; and

a fourth active fin substantially parallel to the second active fin, the second active fin spaced from the fourth active fin with a second fin pitch smaller than the first fin pitch.

4. The semiconductor device of claim 3, further comprising:

a second fin stub on the substrate, wherein the second fin stub connects a bottom portion of the third active fin and a bottom portion of the fourth active fin, and the second fin stub is lower than the isolation feature in height.

5. The semiconductor device of claim 1, further comprising:

a third active fin substantially parallel to the first active fin, the first active fin spaced from the third active fin with a first fin pitch; and

multiple fourth active fins substantially parallel to the second active fin, fins of the second active fin and the fourth active fins being spaced from each other with a second fin pitch smaller than the first fin pitch.

6. The semiconductor device of claim 5, further comprising:

a second fin stub on the substrate, wherein the second fin stub connects a bottom portion of the third active fin and a bottom portion of one of the fourth active fins, and the second fin stub is lower than the isolation feature in height.

7. The semiconductor device of claim 6, wherein the first fin stub and the second fin stub are oriented lengthwise along two nonparallel directions.

8. The semiconductor device of claim 5, further comprising:

a second fin stub on the substrate, wherein the second fin stub connects a bottom portion of one of the fourth active fins and a bottom portion of another one of the fourth active fins, and the second fin stub is lower than the isolation feature in height.

9. The semiconductor device of claim 1, wherein:

the isolation feature includes silicon oxide; and

the first and second active fins and the first fin stub include silicon.

10. A semiconductor device, comprising:

a first fin on a substrate, wherein the first fin provides source, drain, and channel regions for a first field effect transistor (FET);

a second fin on the substrate, wherein the second fin provides source, drain, and channel regions for a second FET;

a first fin stub on the substrate, wherein the first fin stub connects a bottom portion of the first fin and a bottom portion of the second fin; and

an isolation feature over the first fin stub and between the first and second fins, wherein a top surface of the isolation feature is above a top surface of the first fin stub and is below top surfaces of the first and second fins,

wherein from a top view, the first and second fins are oriented lengthwise in a first direction, and the first fin stub is oriented lengthwise in a second direction that is different from the first direction.

11. The semiconductor device of claim 10, wherein the isolation feature includes silicon oxide, and wherein the first and second fins and the first fin stub include silicon.

12. The semiconductor device of claim 10, wherein the first and second directions form an angle not more than 45 degrees.

13. The semiconductor device of claim 10, further comprising:

a third fin substantially parallel to the first fin and spaced from the first fin with a first fin pitch; and

multiple fourth fins substantially parallel to the second fin, fins of the second fin and the fourth fins being spaced from each other with a second fin pitch smaller than the first fin pitch.

14. The semiconductor device of claim 13, further comprising:

a second fin stub on the substrate, wherein the second fin stub connects a bottom portion of the third fin and a bottom portion of one of the fourth fins, wherein a top surface of the second fin stub is lower than the top surface of the isolation feature.

15. The semiconductor device of claim 14, wherein the first fin stub and the second fin stub are oriented lengthwise along two different directions.

16. The semiconductor device of claim 14, further comprising:

a third fin stub on the substrate, wherein the third fin stub connects a bottom portion of one of the fourth fins and a bottom portion of another one of the fourth fins, wherein a top surface of the third fin stub is lower than the top surface of the isolation feature.

17. A semiconductor device, comprising:

first fins on a substrate, oriented lengthwise generally along a first direction, and spaced from each other with a first fin pitch along a second direction perpendicular to the first direction;

second fins on the substrate, oriented lengthwise generally along the first direction, and spaced from each other with a second fin pitch along the second direction, wherein the second fin pitch is smaller than the first fin pitch;

a first fin stub on the substrate, wherein the first fin stub connects a bottom portion of one of the first fins and a bottom portion of one of the second fins, wherein the first fin stub is oriented lengthwise along a third direction that is different from the first and second directions; and

an isolation feature covering the first fin stub, wherein a top surface of the isolation feature is lower than top surfaces of the first and second fins.

18. The semiconductor device of claim 17, wherein each of the first and second fins and the first fin stub includes silicon.

19. The semiconductor device of claim 17, further comprising:

a second fin stub on the substrate, wherein the second fin stub connects a bottom portion of another one of the first fins and a bottom portion of another one of the second fins, wherein the second fin stub is oriented lengthwise along a fourth direction that is different from the first, second, and third directions.

20. The semiconductor device of claim 19, wherein the first and third directions form an angle not more than 45 degrees, and the first and fourth directions form another angle not more than 45 degrees.