Edge test and depth calculation in graphics processing hardware

• US 10,521,950 B2
• Filed: 05/16/2018
• Issued: 12/31/2019
• Est. Priority Date: 04/05/2018
• Status: Active Grant

• Current Assignee: Imagination Technologies Limited (Imagination Technologies Group Ltd.)
• Original Assignee: Imagination Technologies Limited (Imagination Technologies Group Ltd.)
• Inventors: Van Benthem, Casper
• Primary Examiner(s): Mushambo, Martin
• Application Number:
  US15/981,102
• Publication Number:
  US 20190311516A1
• Time in Patent Office: 594 Days
• Field of Search: None
• CPC Class Codes: G06T 11/40 Filling a planar surface by adding surface attributes, e.g. colour or texture
• CPC Class Codes: G06T 15/005 General purpose rendering architectures
• CPC Class Codes: G06T 17/20 Finite element generation, e.g. wire-frame surface description, tesselation
• CPC Class Codes: G06T 2200/12 involving antialiasing
• CPC Class Codes: G06T 2210/36 Level of detail

Abstract

A graphics processing hardware pipeline is arranged to perform an edge test or a depth calculation. Each hardware arrangement includes a microtile component hardware element, multiple pixel component hardware elements, one or more subsample component hardware elements and a final addition and comparison unit. The microtile component hardware element calculates a first output using a sum-of-products and coordinates of a microtile within a tile in the rendering space. Each pixel component hardware element calculates a different second output using the sum-of-products and coordinates for different pixels defined relative to an origin of the microtile. The subsample component hardware element calculates a third output using the sum-of-products and coordinates for a subsample position defined relative to an origin of a pixel. The adders sum different combinations of the first output, a second output and a third output to generate output results for different subsample positions defined relative to the origin of the tile.

Claims

1. A graphics processing pipeline arranged to render a scene in a rendering space, wherein the rendering space is sub-divided into a plurality of tiles, each tile is sub-divided into a plurality of microtiles, each microtile comprising an identical arrangement of pixels and each pixel comprising an arrangement of one or more subsample positions,

the graphics processing pipeline comprising edge test and/or depth calculation hardware and wherein the edge test and/or depth calculation hardware comprises one or more hardware arrangements each arranged to perform an edge test or a depth calculation using a sum-of-products, wherein the sum-of-products corresponds to a property of a primitive representing a surface of an object in the scene, each hardware arrangement comprising:

a microtile component hardware element comprising hardware logic arranged to calculate a first output using the sum-of-products and coordinates of a microtile within a tile in the rendering space;

a plurality of pixel component hardware elements, each comprising hardware logic arranged to calculate one of a plurality of second outputs using the sum-of-products and coordinates for different pixels defined relative to an origin of the microtile;

one or more subsample component hardware elements, each comprising hardware logic arranged to calculate a third output using the sum-of-products and coordinates for a subsample position defined relative to an origin of a pixel; and

a plurality of adders arranged to generate a plurality of output results for the sum-of products in parallel by combining, for each output result, a different combination of the first output, one of the plurality of second outputs and a third output, wherein the plurality of output results comprise edge test output values or depth calculation values for rendering subsamples;

wherein the scene is rendered in said rendering space using the generated edge test output values or depth calculation values.

2. The graphics processing pipeline according to claim 1, wherein each pixel comprises a plurality of subsample positions and each hardware arrangement comprises a plurality of subsample component hardware elements, each comprising hardware logic arranged to calculate one of a plurality of third outputs using the sum-of-products and coordinates for different subsample positions defined relative to an origin of a pixel.

3. The graphics processing pipeline according to claim 1, wherein one or more of the hardware arrangements further comprises:

a plurality of multiplexers arranged to select the different combinations of the first output, one of the plurality of second outputs and a third output.

4. The graphics processing pipeline according to claim 1, wherein the plurality of adders comprise:

a plurality of addition and comparison elements, each addition and comparison element arranged to generate a different one of the plurality of output results by combining a different combination of the first output, one of the plurality of second outputs and a third output.

5. The graphics processing pipeline according to claim 4, wherein each pixel comprises a plurality of subsample positions and each hardware arrangement comprises a plurality of subsample component hardware elements, each comprising hardware logic arranged to calculate one of a plurality of third outputs using the sum-of-products and coordinates for different subsample positions defined relative to an origin of a pixel and wherein one or more of the hardware arrangements further comprises a first plurality of multiplexers, each of the multiplexers in the first plurality of multiplexers having a plurality of inputs and an output, wherein each input is arranged to receive a different one of the plurality of second outputs from the plurality of pixel component hardware elements and the multiplexer is arranged to select one of the received second outputs and output the selected second output to one of the plurality of addition and comparison elements via the output.

6. The graphics processing pipeline according to claim 4, wherein the one or more of the hardware arrangements further comprises a second plurality of multiplexers, each of the multiplexers in the second plurality of multiplexers having a plurality of inputs and an output, wherein each input is arranged to receive a different one of the plurality of third outputs from the plurality of subsample component hardware elements and the multiplexer is arranged to select one of the received third outputs and output the selected third output to one of the plurality of addition and comparison elements via the output.

7. The graphics processing pipeline according to claim 1, wherein the plurality of adders comprises a first subset of the plurality of adders and a second subset of the plurality of adders,

wherein each of the pixel component hardware elements further comprises an input for receiving the first output from the microtile component hardware element and at least one of the first subset of the plurality of adders arranged to sum the first output received from the microtile component hardware element and the second output calculated by the pixel component hardware element to generate an intermediate result, and

wherein the second subset of the plurality of adders comprises:

a plurality of addition and comparison elements, each addition and comparison element arranged to generate a different one of the plurality of output results by summing a different combination of one of the intermediate results and a third output.

8. The graphics processing pipeline according to claim 7, wherein one or more of the hardware arrangements further comprises a first plurality of multiplexers, each of the multiplexers in the first plurality of multiplexers having a plurality of inputs and an output, wherein each input is arranged to receive a different one of the intermediate results from the plurality of pixel component hardware elements and the multiplexer is arranged to select one of the received intermediate results and output the selected intermediate result to one of the plurality of addition and comparison elements via the output.

9. The graphics processing pipeline according to claim 7, wherein each pixel comprises a plurality of subsample positions and each hardware arrangement comprises a plurality of subsample component hardware elements, each comprising hardware logic arranged to calculate one of a plurality of third outputs using the sum-of-products and coordinates for different subsample positions defined relative to an origin of a pixel and wherein one or more of the hardware arrangements further comprises a second plurality of multiplexers, each of the multiplexers in the second plurality of multiplexers having a plurality of inputs and an output, wherein each input is arranged to receive a different one of a plurality of third outputs from the plurality of subsample component hardware elements and the multiplexer is arranged to select one of the received third outputs and output the selected third output to one of the plurality of addition and comparison elements via the output.

10. The graphics processing pipeline according to claim 1, wherein the edge test and/or depth calculation hardware comprises at least one hardware arrangement arranged to perform an edge test, wherein the sum-of-products corresponds to an edge vector of a primitive.

11. The graphics processing pipeline according to claim 10, wherein the edge test and/or depth calculation hardware comprises a plurality of hardware arrangements arranged to perform an edge test, wherein the sum-of-products for each of the plurality of hardware arrangements corresponds to a different edge vector of a single primitive.

12. The graphics processing pipeline according to claim 10, further comprising a decision unit, the decision unit comprising an input for receiving the first output from the microtile component hardware element and hardware logic arranged to determine whether any combination of a second output and a third output, when added to the first output, could result in an output result having a different sign to the first output, and in response to determining that the combination could not result in an output having a different sign to the first output, to output a most significant bit of the first output.

13. The graphics processing pipeline according to claim 1, wherein the edge test and/or depth calculation hardware comprises at least one hardware arrangement arranged to perform a depth calculation, wherein the sum-of-products corresponds to a depth equation of a primitive.

14. The graphics processing pipeline according to claim 1, wherein the edge test and/or depth calculation hardware comprises a hardware arrangement arranged to perform a depth calculation and a plurality of hardware arrangements arranged to perform an edge test, wherein the sum-of-products used in the hardware arrangement arranged to perform a depth calculation corresponds to a depth equation of a primitive, and the sum-of-products used in each of the hardware arrangements arranged to perform an edge test corresponds to a different edge vector of the primitive.

15. The graphics processing pipeline according to claim 14, wherein the primitive comprises pairs of parallel edge vectors and the two hardware arrangements arranged to perform edge tests corresponding to each of a pair of parallel edge vectors comprise shared pixel component hardware elements and shared subsample component hardware elements, such that the second outputs and the third outputs are each calculated once for each pixel within a microtile and each subsample within a pixel and used by both hardware arrangements.

16. The graphics processing pipeline according to claim 1, wherein the graphics processing pipeline operates in one of a plurality of operating modes, each operating mode corresponding to a different arrangement of one or more subsample positions within each pixel and wherein the plurality of adders are arranged to generate a plurality of output results for the sum-of-products in parallel by combining, for each output result, a different combination of the first output, one of the plurality of second outputs and a third output calculated using coordinates for a subsample position in the arrangement of subsample positions for a current operating mode.

17. A method of rendering a scene in a rendering space in a graphics processing pipeline, wherein the rendering space is sub-divided into a plurality of tiles, each tile is sub-divided into a plurality of microtiles, each microtile comprising an identical arrangement of pixels and each pixel comprising one or more subsample positions, the method comprising:

in a first hardware element, determining a first output based on coordinates of a microtile within a tile;

in each of a plurality of second hardware elements, determining a second output based on coordinates of a pixel within a microtile;

in each of one or more third hardware elements, determining a third output based on coordinates of a subsample within a pixel;

combining a first output with a second output and a third output to generate an edge test output value or a depth calculation value for rendering a subsample; and

rendering the scene in said rendering space using the generated edge test output value or depth calculation value.

18. The method of claim 17, wherein a plurality of edge test output values or depth calculation values are generated in parallel by combining, in each of a plurality of addition and comparison elements, a different combination of the first output, a second output and a third output.

19. The method of claim 18, further comprising either:

determining whether there are more possible combinations of the first output, a second output and a third output than addition and comparison elements; and

in response to determining that there are more possible combinations of the first output, a second output and a third output than addition and comparison elements, selecting a mode of operation with a reduced size of a microtile such that it comprises fewer pixels;

or;

determining whether there are more possible combinations of the first output, a second output and a third output than addition and comparison elements; and

in response to determining that there are more possible combinations of the first output, a second output and a third output than addition and comparison elements, generating an edge test output value or depth calculation value from each of a first subset of the possible combinations in a first clock cycle and generating an edge test output value or depth calculation value from each of a second subset of the possible combinations in a second clock cycle, wherein the first and second subsets are non-overlapping.

20. A non-transitory computer readable storage medium having stored thereon a computer readable description of an integrated circuit that, when processed in an integrated circuit manufacturing system, causes the integrated circuit manufacturing system to manufacture a graphics processing pipeline arranged to render a scene in a rendering space, wherein the rendering space is sub-divided into a plurality of tiles, each tile is sub-divided into a plurality of microtiles, each microtile comprising an identical arrangement of pixels and each pixel comprising an arrangement of one or more subsample positions,

the graphics processing pipeline comprising edge test and/or depth calculation hardware and wherein the edge test and/or depth calculation hardware comprises one or more hardware arrangements each arranged to perform an edge test or a depth calculation using a sum-of-products, wherein the sum-of-products corresponds to a property of a primitive representing a surface of an object in the scene, each hardware arrangement comprising:

a microtile component hardware element comprising hardware logic arranged to calculate a first output using the sum-of-products and coordinates of a microtile within a tile in the rendering space;

a plurality of pixel component hardware elements, each comprising hardware logic arranged to calculate one of a plurality of second outputs using the sum-of-products and coordinates for different pixels defined relative to an origin of the microtile;

one or more subsample component hardware elements, each comprising hardware logic arranged to calculate a third output using the sum-of-products and coordinates for a subsample position defined relative to an origin of a pixel; and

a plurality of adders arranged to generate a plurality of output results for the sum-of products in parallel by combining, for each output result, a different combination of the first output, one of the plurality of second outputs and a third output, wherein the plurality of output results comprise edge test output values or depth calculation values for rendering subsamples;

wherein the scene is rendered in said rendering space using the generated edge test output values or depth calculation values.