Forwarding signal supply voltage in data transmission system

• US 10,522,194 B2
• Filed: 10/01/2018
• Issued: 12/31/2019
• Est. Priority Date: 08/31/2009
• Status: Active Grant

• Current Assignee: Rambus Inc.
• Original Assignee: Rambus Inc.
• Inventors: Best, Scott C., Poulton, John W.
• Primary Examiner(s): Shah, Tanmay K
• Application Number:
  US16/148,491
• Publication Number:
  US 20190139583A1
• Time in Patent Office: 456 Days
• Field of Search: 375285
• CPC Class Codes: G06F 11/0727 in a storage system, e.g. in a DASD or network based storage system drivers for digital recording or reproducing units G06F3/06; circuits for error detection or correction within digital recording or reproducing units G11B20/18; for distributed storage of data in networks, e.g. transport arrangements for network file system [NFS], storage area networks [SAN] or network attached storage [NAS], H04L67/1097
• CPC Class Codes: G06F 11/076 by exceeding a count or rate limit, e.g. word- or bit count limit
• CPC Class Codes: G06F 11/0793 Remedial or corrective actions recovery from an exception in an instruction pipeline G06F9/3861; by retry G06F11/1402; for recovering from a failure of a protocol instance or entity H04L69/40
• CPC Class Codes: G06F 13/4072 Drivers or receivers G06F13/4086 takes precedence; for multistate logic circuits H03K19/0002
• CPC Class Codes: G11C 5/144 Detection of predetermined disconnection or reduction of power supply, e.g. power down or power standby
• CPC Class Codes: G11C 5/145 Applications of charge pumps; Boosted voltage circuits; Clamp circuits therefor G11C5/141 takes precedence
• CPC Class Codes: H04L 1/203 Details of error rate determination, e.g. BER, FER or WER
• CPC Class Codes: H04L 25/0264 Arrangements for coupling to transmission lines duplexing arrangements H04L5/14; line equalisers, line build-out devices H04L25/03878
• CPC Class Codes: H04L 25/08 Modifications for reducing interference; Modifications for reducing effects due to line faults ; Receiver end arrangements for detecting or overcoming line faults

Abstract

In a data transmission system, one or more signal supply voltages for generating the signaling voltage of a signal to be transmitted are generated in a first circuit and forwarded from the first circuit to a second circuit. The second circuit may use the forwarded signal supply voltages to generate another signal to be transmitted back from the second circuit to the first circuit, thereby obviating the need to generate signal supply voltages separately in the second circuit. The first circuit may also adjust the signal supply voltages based on the signal transmitted back from the second circuit to the first circuit. The data transmission system may employ a single-ended signaling system in which the signaling voltage is referenced to a reference voltage that is a power supply voltage such as ground, shared by the first circuit and the second circuit.

Claims

1. A multi-chip memory device comprising:

a first chip including;

a voltage generator configured to generate a signal supply voltage;

at least a first electrical connection to forward, to at least a second chip, the signal supply voltage; and

,

a receiver configured to receive, via a second electrical connection, a first signal having a signal swing dependent on the signal supply voltage;

the second chip including;

at least a second electrical connection configured to receive the signal supply voltage forwarded from the first chip; and

a transmitter configured to transmit, via the second electrical connection, the first signal having a signal swing dependent on the signal supply voltage.

2. The multi-chip memory device of claim 1, wherein the first chip further comprises:

a transmitter configured to transmit, via the second electrical connection, a second signal having a signal swing dependent on the signal supply voltage.

3. The multi-chip memory device of claim 1, wherein the second chip further comprises:

a receiver configured to receive, via the second electrical connection, a second signal having a signal swing dependent on the signal supply voltage.

4. The multi-chip memory device of claim 2, wherein the second chip further comprises:

a receiver configured to receive, via the second electrical connection, a second signal having a signal swing dependent on the signal supply voltage.

5. The multi-chip memory device of claim 1, wherein the first electrical connection and the second electrical connection comprise through-silicon vias (TSVs).

6. The multi-chip memory device of claim 5, wherein the first chip and the second chip are within the same multi-die package.

7. The multi-chip memory device of claim 5, wherein the first electrical connection and the second electrical connection further electrically connect to a plurality of chips.

8. The multi-chip memory device of claim 7, wherein the plurality of chips are arranged in a stack.

9. The multi-chip memory device of claim of claim 1, wherein the voltage generator comprises at least one charge pump.

10. A multi-die package, comprising:

a first integrated circuit that includes one or more voltage generators configured to generate at least one signal supply voltage, a first off-die connection point to couple the at least one signal supply voltage to at least a second integrated circuit in the multi-die package, and, a receiver configured to receive a first signal having a signal swing based at least in part on the at least one signal supply voltage;

a second integrated circuit includes a transmitter configured to transmit, to the first integrated circuit, the first signal, the first signal to have a signal swing based at least in part on a received version of the at least one signal supply voltage.

11. The multi-die package of claim 10, wherein the first integrated circuit and the second integrated circuit are part of a plurality of integrated circuit dies arranged in a stack.

12. The multi-die package of claim 10, wherein the second integrated circuit includes a second off-die connection point to couple the at least one signal supply voltage to at least a third integrated circuit in the multi-die package.

13. The multi-die package of claim 12, wherein the second integrated circuit includes at least one through-silicon via to connect the received version of the at least one signal supply voltage to second off-die connection point.

14. The multi-die package of claim 10, wherein the second integrated circuit is a memory device.

15. The multi-die package of claim 10, wherein the second integrated circuit is a DRAM memory device.

16. The multi-die package of claim 10, wherein the first integrated circuit further comprises:

a transmitter configured to transmit, via the first off-die connection point, a second signal having a signal swing based at least in part on the at least one signal supply voltage.

17. The multi-die package of claim 10, wherein the one or more voltage generators comprise at least one charge pump.

18. An integrated circuit, comprising:

at least a first DRAM circuit;

a first signal supply connection to receive, from a second integrated circuit having one or more voltage generators configured to a signal supply voltage, the signal supply voltage;

a first transmitter to transmit, to the second integrated circuit, a first signal that has a signal swing based at least in part of the signal supply voltage; and

,

a through-silicon via to forward, to a third integrated circuit, the signal supply voltage.

19. The integrated circuit of claim 18, further comprising:

a receiver to receive, from the second integrated circuit, a second signal that has a signal swing based at least in part of the signal supply voltage.

20. The integrated circuit of claim 19, wherein the second signal is produced by a second transmitter on the second integrated circuit that receives the signal supply voltage.