Apparatuses and method for reducing row address to column address delay

• US 10,522,205 B1
• Filed: 06/20/2018
• Issued: 12/31/2019
• Est. Priority Date: 06/20/2018
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Kawamura, Christopher
• Primary Examiner(s): Yang, Han
• Application Number:
  US16/013,618
• Publication Number:
  US 20190392877A1
• Time in Patent Office: 559 Days
• Field of Search: 36518521, 365205, 365207
• CPC Class Codes: G11C 11/4076 Timing circuits for regeneration management G11C11/406
• CPC Class Codes: G11C 11/4091 Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
• CPC Class Codes: G11C 11/4094 Bit-line management or control circuits
• CPC Class Codes: G11C 2207/002 Isolation gates, i.e. gates coupling bit lines to the sense amplifier
• CPC Class Codes: G11C 7/065 Differential amplifiers of latching type
• CPC Class Codes: G11C 7/08 Control thereof
• CPC Class Codes: G11C 7/12 Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
• CPC Class Codes: G11C 8/10 Decoders
• CPC Class Codes: G11C 8/18 Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals

Abstract

Apparatuses and methods for reducing row address (RAS) to column address (CAS) delay are disclosed. An example apparatus includes a memory including a memory cell coupled to a first digit line in response to a wordline being set to an active state and a sense amplifier coupled to the first digit line and to a second digit line. The sense amplifier is configured to perform a threshold voltage compensation operation to bias the first digit line and the second digit line based on a threshold voltage difference between at least two circuit components of the sense amplifier. The apparatus further comprising a decoder circuit coupled to the wordline and to the sense amplifier. In response to an activate command, the decoder circuit is configured to initiate the threshold voltage compensation operation and, during the threshold voltage compensation operation, to the set the wordline to the active state.

Claims

1. An apparatus comprising:

a memory comprising;

a memory cell coupled to a first digit line in response to a wordline being set to an active state;

a sense amplifier coupled to the first digit line and to a second digit line, wherein the sense amplifier is configured to perform a threshold voltage compensation operation to bias the first digit line and the second digit line based on a threshold voltage difference between at least two circuit components of the sense amplifier, wherein the at least two circuit components include a first transistor coupled between the first gut node and a row Nsense latch (RNL) signal and a second transistor coupled between the second gut node and the RNL signal;

a decoder circuit coupled to the wordline and to the sense amplifier, wherein, in response to an activate command, the decoder circuit is configured to initiate the threshold voltage compensation operation and, during the threshold voltage compensation operation, to the set the wordline to the active state,

wherein, during the threshold voltage compensation operation, a first gut node of the sense amplifier is coupled to the second digit line via a third transistor and a second gut node of the sense amplifier is coupled to the first digit line via a fourth transistor.

2. The apparatus of claim 1, wherein the decoder circuit is configured to stop the threshold voltage compensation operation after the wordline is set to the active state.

3. The apparatus of claim 2, wherein the decoder circuit is configured to stop the threshold voltage compensation operation less than 3 nanoseconds after the wordline is set to the active state.

4. The apparatus of claim 2, wherein the decoder circuit is configured to stop the threshold voltage compensation operation between 0.25 and 1.25 nanoseconds and after the wordline is set to the active state.

5. The apparatus of claim 1, wherein, during the threshold voltage compensation operation, the decoder circuit is configured to set a bit line compensation control signal to enable the third and fourth transistors.

6. The apparatus of claim 1, wherein a gate of the first transistor is coupled to the second digit line and a gate of the second transistor is coupled to the first digit line, the apparatus further comprising:

a fifth transistor having a gate coupled to the first digit line and a source coupled to a row Psense latch (ACT) signal, wherein a drain of the fifth transistor is coupled to the second gut node; and

a sixth transistor having a gate coupled to the second digit line and a source coupled to the ACT signal, wherein a drain of the fifth transistor is coupled to the first gut node.

7. The apparatus of claim 6, wherein the sense amplifier further comprises:

a seventh transistor configured to decouple the first digit line from the first gut node during the threshold voltage compensation operation; and

an eighth transistor configured to decouple the second digit line from the second gut node during the threshold voltage compensation operation.

8. An apparatus including:

a sense amplifier configured to, prior to performing a sense operation associated with a memory cell, perform a threshold voltage compensation operation to bias a first digit line and a second digit line such that a voltage difference between the first digit line and the second digit line is equal to a threshold voltage difference between at least two circuit components of the sense amplifier;

a wordline coupled to the memory cell, wherein the wordline is set to an active state during the threshold voltage compensation operation; and

a decoder circuit configured to set the wordline to the active state during the threshold voltage compensation operation based on an activation command, wherein the decoder circuit is configured to set the wordline to the active state at least 0.25 nanoseconds before an end of the threshold voltage compensation operation.

9. The apparatus of claim 8, wherein the decoder circuit includes a row decoder.

10. The apparatus of claim 8, wherein the decoder circuit is configured to stop the threshold voltage compensation operation between and including 3 and 0.25 nanoseconds before the end of the threshold voltage compensation operation.

11. The apparatus of claim 8, wherein, after the threshold voltage compensation operation, latching the first digit line and the second digit line to respective voltages based on sensed data stored at the memory cell.

12. A method, comprising:

receiving an activate command at a memory;

in response to the activate command, performing a threshold voltage compensation operation to bias digit lines coupled to a sense amplifier of the memory based on a threshold voltage difference between at least two circuit components of the sense amplifier;

during the threshold voltage compensation operation, activating a wordline based on the activate command, wherein activation of the wordline based on the activate command is between and including 0.25 and 3 nanoseconds before an end of the threshold voltage compensation operation; and

after the threshold voltage operation, sensing data of a memory cell at the sense amplifier, wherein the memory cell is coupled to a digit line of the digit lines in response to activation of the wordline.

13. The method of claim 12, wherein performing the threshold voltage compensation operation to bias the digit lines coupled to the sense amplifier is based on threshold voltage differences between a first n-type transistor and a second n-type transistor of the sense amplifier.

14. The method of claim 12, further comprising sensing data of a memory cell coupled to the word line at a predetermined time after activation of the wordline.