Apparatuses and method for reducing row address to column address delay
First Claim
1. An apparatus comprising:
- a memory comprising;
a memory cell coupled to a first digit line in response to a wordline being set to an active state;
a sense amplifier coupled to the first digit line and to a second digit line, wherein the sense amplifier is configured to perform a threshold voltage compensation operation to bias the first digit line and the second digit line based on a threshold voltage difference between at least two circuit components of the sense amplifier, wherein the at least two circuit components include a first transistor coupled between the first gut node and a row Nsense latch (RNL) signal and a second transistor coupled between the second gut node and the RNL signal;
a decoder circuit coupled to the wordline and to the sense amplifier, wherein, in response to an activate command, the decoder circuit is configured to initiate the threshold voltage compensation operation and, during the threshold voltage compensation operation, to the set the wordline to the active state,wherein, during the threshold voltage compensation operation, a first gut node of the sense amplifier is coupled to the second digit line via a third transistor and a second gut node of the sense amplifier is coupled to the first digit line via a fourth transistor.
3 Assignments
0 Petitions
Accused Products
Abstract
Apparatuses and methods for reducing row address (RAS) to column address (CAS) delay are disclosed. An example apparatus includes a memory including a memory cell coupled to a first digit line in response to a wordline being set to an active state and a sense amplifier coupled to the first digit line and to a second digit line. The sense amplifier is configured to perform a threshold voltage compensation operation to bias the first digit line and the second digit line based on a threshold voltage difference between at least two circuit components of the sense amplifier. The apparatus further comprising a decoder circuit coupled to the wordline and to the sense amplifier. In response to an activate command, the decoder circuit is configured to initiate the threshold voltage compensation operation and, during the threshold voltage compensation operation, to the set the wordline to the active state.
-
Citations
14 Claims
-
1. An apparatus comprising:
a memory comprising; a memory cell coupled to a first digit line in response to a wordline being set to an active state; a sense amplifier coupled to the first digit line and to a second digit line, wherein the sense amplifier is configured to perform a threshold voltage compensation operation to bias the first digit line and the second digit line based on a threshold voltage difference between at least two circuit components of the sense amplifier, wherein the at least two circuit components include a first transistor coupled between the first gut node and a row Nsense latch (RNL) signal and a second transistor coupled between the second gut node and the RNL signal; a decoder circuit coupled to the wordline and to the sense amplifier, wherein, in response to an activate command, the decoder circuit is configured to initiate the threshold voltage compensation operation and, during the threshold voltage compensation operation, to the set the wordline to the active state, wherein, during the threshold voltage compensation operation, a first gut node of the sense amplifier is coupled to the second digit line via a third transistor and a second gut node of the sense amplifier is coupled to the first digit line via a fourth transistor. - View Dependent Claims (2, 3, 4, 5, 6, 7)
-
8. An apparatus including:
-
a sense amplifier configured to, prior to performing a sense operation associated with a memory cell, perform a threshold voltage compensation operation to bias a first digit line and a second digit line such that a voltage difference between the first digit line and the second digit line is equal to a threshold voltage difference between at least two circuit components of the sense amplifier; a wordline coupled to the memory cell, wherein the wordline is set to an active state during the threshold voltage compensation operation; and a decoder circuit configured to set the wordline to the active state during the threshold voltage compensation operation based on an activation command, wherein the decoder circuit is configured to set the wordline to the active state at least 0.25 nanoseconds before an end of the threshold voltage compensation operation. - View Dependent Claims (9, 10, 11)
-
-
12. A method, comprising:
-
receiving an activate command at a memory; in response to the activate command, performing a threshold voltage compensation operation to bias digit lines coupled to a sense amplifier of the memory based on a threshold voltage difference between at least two circuit components of the sense amplifier; during the threshold voltage compensation operation, activating a wordline based on the activate command, wherein activation of the wordline based on the activate command is between and including 0.25 and 3 nanoseconds before an end of the threshold voltage compensation operation; and after the threshold voltage operation, sensing data of a memory cell at the sense amplifier, wherein the memory cell is coupled to a digit line of the digit lines in response to activation of the wordline. - View Dependent Claims (13, 14)
-
Specification