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Semiconductor device and system

  • US 10,522,206 B2
  • Filed: 04/06/2018
  • Issued: 12/31/2019
  • Est. Priority Date: 04/06/2017
  • Status: Active Grant
First Claim
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1. A semiconductor device comprising:

  • a first buffer configured to buffer a first input signal and a second input signal to generate a first data strobe buffering signal and a first data strobe bar buffering signal;

    a second buffer configured to generate a second data strobe buffering signal based on the first input signal and a reference voltage;

    a divider circuit configured to divide the second data strobe buffering signal to generate a divided signal and a divided bar signal; and

    an internal signal generation circuit configured to generate a first data latch timing signal, a second data latch timing signal, a third data latch timing signal and a fourth data latch timing signal having different phases based on the first data strobe buffering signal, the first data strobe bar buffering signal, the divided signal and the divided bar signal.

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