Resistive memory device for matrix-vector multiplications

• US 10,522,223 B1
• Filed: 07/04/2018
• Issued: 12/31/2019
• Est. Priority Date: 07/04/2018
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Le Gallo-Bourdeau, Manuel, Sebastian, Abu, Kull, Lukas
• Primary Examiner(s): Bashar, Mohammed A
• Application Number:
  US16/027,347
• Publication Number:
  US 20200013462A1
• Time in Patent Office: 545 Days
• CPC Class Codes: G06G 7/163 using a variable impedance controlled by one of the input signals, variable amplification or transfer function G06G7/161, G06G7/162 take precedence
• CPC Class Codes: G11C 11/54 using elements simulating biological cells, e.g. neuron
• CPC Class Codes: G11C 13/0004 comprising amorphous/crystalline phase transition cells
• CPC Class Codes: G11C 13/0023 Address circuits or decoders
• CPC Class Codes: G11C 13/0026 Bit-line or column circuits
• CPC Class Codes: G11C 13/0028 Word-line or row circuits
• CPC Class Codes: G11C 13/003 Cell access
• CPC Class Codes: G11C 13/004 Reading or sensing circuits or methods
• CPC Class Codes: G11C 13/0061 Timing circuits or methods
• CPC Class Codes: G11C 13/0069 Writing or programming circuits or methods
• CPC Class Codes: G11C 2213/15 Current-voltage curve
• CPC Class Codes: G11C 2213/52 Structure characterized by the electrode material, shape, etc.
• CPC Class Codes: G11C 2213/53 Structure wherein the resistive material being in a transistor, e.g. gate
• CPC Class Codes: G11C 2213/73 Array where access device function, e.g. diode function, being merged with memorizing function of memory element
• CPC Class Codes: G11C 2213/74 Array wherein each memory cell has more than one access device
• CPC Class Codes: G11C 2213/76 Array using an access device for each cell which being not a transistor and not a diode
• CPC Class Codes: G11C 2213/79 Array wherein the access device being a transistor

Abstract

A matrix-vector multiplication device includes a memory crossbar array with row lines, column lines, and junctions. Each junction comprises a programmable resistive element and an access element. A signal generator is configured to apply programming signals to the resistive elements to program conductance values for the matrix-vector multiplication and a readout circuit is configured to apply read voltages to the row lines and to read out current values of the column lines. Control circuitry is configured to control the signal generator and the readout circuit and to select, via the access terminals, a plurality of resistive elements in parallel according to a predefined selection scheme which applies the signals and/or the read voltages in parallel to resistive elements which do not share the same row and column line and applies the programming signals and/or the read voltages to at most one resistive element per row line and column line.

Claims

1. A memcomputing device for performing a matrix-vector multiplication of a matrix with a vector, the device comprising:

a memory crossbar array comprising

a plurality of row lines;

a plurality of column lines;

a plurality of junctions arranged between the plurality of row lines and the plurality of column lines, wherein each junction comprises a programmable resistive element and an access element comprising an access terminal for accessing the programmable resistive element;

a signal generator configured to

apply programming signals to the resistive elements to program conductance values representing respective elements of the matrix to be multiplied with the vector;

a readout circuit configured to

apply read voltages to the row lines of the memory crossbar array, wherein the read voltages represent respective elements of the vector to be multiplied with the matrix;

read out current values of the column lines of the memory crossbar array, wherein the current values represent respective elements of a product of the matrix-vector multiplication; and

control circuitry configured to control the signal generator and the readout circuit and to select by means of the access terminals a plurality of resistive elements in parallel according to a predefined selection scheme, wherein the predefined selection scheme is configured to

apply the programming signals and/or the read voltages in parallel to a plurality of resistive elements which do not share the same row line nor the same column line; and

apply the programming signals and/or the read voltages to at most one resistive element per row line and at most one resistive element per column line.

2. The device according to claim 1, wherein the device comprises access circuitry configured to apply in parallel a selection signal to a subset of the access terminals to select in parallel a subset of the resistive elements according to the predefined selection scheme.

3. The device according to claim 1, wherein the junctions comprise a serial arrangement of a resistive element and an access transistor comprising a gate as access terminal.

4. The device according to claim 1, wherein the resistive element is embodied as projected memory, the projected memory comprising an integrated access terminal.

5. The device according to claim 1, wherein the selection scheme is configured to select in parallel resistive elements of one or more diagonals of the memory crossbar array.

6. The device according to claim 5, wherein the device comprises a plurality of diagonal access lines, wherein each of the plurality of diagonal access lines is coupled to the access terminals of an array of diagonally arranged resistive elements.

7. The device according to claim 1, wherein the device comprises a plurality of column access lines, the column access lines being arranged along the column lines of the memory crossbar array, wherein each of the plurality of column access lines is coupled to the access terminals of an array of resistive elements being arranged in a column line.

8. The device according to claim 7, wherein the selection scheme is configured to apply programming signals and/or read voltages only to access terminals of row lines which do not share the same column access lines.

9. The device according to claim 1, wherein the junctions comprise a serial arrangement of a resistive element and an access transistor comprising a gate as access terminal, and wherein the device comprises a plurality of memory blocks, and wherein an output of each memory block is coupled to at least one access transistor.

10. The device according to claim 9, wherein the memory blocks are embodied as flip-flops.

11. The device according to claim 9, wherein the memory blocks are arranged in rows of memory blocks, wherein each row of memory blocks is configured as shift register.

12. The device according to claim 1, wherein an element of the vector is represented as a duration of a read voltage pulse and/or a voltage level of a read voltage pulse.

13. The device according to claim 1, wherein the device is configured

to perform multiple runs for the matrix-vector multiplication;

and

to perform an averaging of result values of the multiple runs.

14. The device as claimed in claim 1, wherein the resistive elements are one of Phase change memory (PCM) elements, Conductive bridge resistive memory elements, Metal-oxide resistive random access memory (RRAM) elements, Magneto-resistive random access memory (MRAM) elements, Ferroelectric random access memory (FeRAM) elements, optical memory elements, and a system device, comprising transistors, resistors, capacitors, and/or inductors, jointly emulating a behavior of a resistive memory element.

15. The device according to claim 1, wherein the signal generator is configured to program the conductance values of the resistive elements by an iterative program and verify procedure.

16. A design structure tangibly embodied in a machine readable medium for designing, manufacturing, or testing an integrated circuit, the design structure comprising:

a memcomputing device for performing a matrix-vector multiplication of a matrix with a vector, the device comprising;

a memory crossbar array comprising

a plurality of row lines;

a plurality of column lines;

a plurality of junctions arranged between the plurality of row lines and the plurality of column lines, wherein each junction comprises a programmable resistive element and an access element comprising an access terminal for accessing the programmable resistive element;

a signal generator configured to

apply programming signals to the resistive elements to program conductance values representing respective elements of the matrix to be multiplied with the vector;

a readout circuit configured to

apply read voltages to the row lines of the memory crossbar array, wherein the read voltages represent respective elements of the vector to be multiplied with the matrix;

read out current values of column lines of the memory crossbar array, wherein the current values represent respective elements of a product of the matrix-vector multiplication; and

control circuitry configured to control the signal generator and the readout circuit and to select by means of the access terminals a plurality of resistive elements in parallel according to a predefined selection scheme, wherein the predefined selection scheme is configured to

apply the programming signals and/or the read voltages in parallel to a plurality of resistive elements which do not share the same row line nor the same column line; and

apply the programming signals and/or the read voltages to at most one resistive element per row line and at most one resistive element per column line.

17. The design structure according to claim 16,

wherein the junctions comprise a serial arrangement of a resistive element and an access transistor comprising a gate as access terminal.

18. The design structure according to claim 16, wherein the resistive element is embodied as projected memory, the projected memory comprising an integrated access terminal.

19. The design structure according to claim 16, wherein the selection scheme is configured to select in parallel resistive elements of one or more diagonals of the memory crossbar array, wherein the device comprises a plurality of diagonal access lines, wherein each of the plurality of diagonal access lines is coupled to the access terminals of an array of diagonally arranged resistive elements.

20. The design structure according to claim 16, wherein the junctions comprise a serial arrangement of a resistive element and an access transistor comprising a gate as access terminal, and wherein the device comprises a plurality of memory blocks, wherein an output of each memory block is coupled to at least one access transistor.