Semiconductor device with non-volatile memory

• US 10,522,225 B1
• Filed: 10/02/2015
• Issued: 12/31/2019
• Est. Priority Date: 10/02/2015
• Status: Active Grant

• Current Assignee: Monolithic 3D, Inc.
• Original Assignee: Monolithic 3D, Inc.
• Inventors: Or-Bach, Zvi, Han, Jin-Woo
• Primary Examiner(s): Ha, Nathan W
• Application Number:
  US14/874,366
• Time in Patent Office: 1,551 Days
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: G11C 11/005 comprising combined but independently operative RAM-ROM, RAM-PROM, RAM-EPROM cells
• CPC Class Codes: G11C 11/5621 using charge storage in a floating gate
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 11/5635 Erasing circuits
• CPC Class Codes: G11C 14/0018 whereby the nonvolatile element is an EEPROM element, e.g. a floating gate or metal-nitride-oxide-silicon [MNOS] transistor
• CPC Class Codes: G11C 16/0475 comprising two or more independent storage sites which store independent data
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/14 Circuits for erasing electrically, e.g. erase voltage switching circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: H01L 21/823431 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 27/0886 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/42344 with at least one additional gate, e.g. program gate, erase gate or select gate
• CPC Class Codes: H01L 29/66977 Quantum effect devices, e.g. using quantum reflection, diffraction or interference effects, i.e. Bragg- or Aharonov-Bohm effects
• CPC Class Codes: H10B 12/20 DRAM devices comprising floating-body transistors, e.g. floating-body cells
• CPC Class Codes: H10B 43/30 characterised by the memory core region

Abstract

A semiconductor device, the device including: a plurality of non-volatile memory cells, where at least one of the non-volatile memory cells includes at least one channel facet, where the at least one channel facet is modified by at least two gates, where the at least one channel facet includes at least two storage locations oriented perpendicular to the at least two gates.

Claims

1. A semiconductor device, the device comprising:

a plurality of non-volatile memory cells and memory control circuits,

wherein at least one of said non-volatile memory cells comprises at least one channel facet,

wherein said at least one channel facet is affected by at least a first gate and a second gate,

wherein said at least one channel facet comprises at least a first storage location and a second storage location such that said first storage location is substantially closer to said first gate and said second storage location is substantially closer to said second gate, and

wherein said first gate and said second gate are independently controlled by said memory control circuits.

2. The semiconductor device according to claim 1,

wherein one of said first gate or said second gate is self-aligned to the other of said first gate or said second gate.

3. The semiconductor device according to claim 1,

wherein said at least one channel facet comprises at least three facets, and

wherein each of said at least three facets has its own charge storage region.

4. The semiconductor device according to claim 1,

wherein said at least one channel facet comprises at least four storage locations.

5. The semiconductor device according to claim 1, further comprising:

a single crystal semiconductor layer overlaying at least a portion of said non-volatile memory cells, and

a plurality of through silicon vias,

wherein said through silicon vias have a radius smaller than 250 nm.

6. The semiconductor device according to claim 1,

wherein said plurality of non-volatile memory cells comprises a first non-volatile memory cell and a non-volatile second memory cell, and

wherein said first non-volatile memory cell and said non-volatile second memory cell also function as volatile floating body memory cells.

7. The semiconductor device according to claim 1, further comprising:

a plurality of volatile memory cells,

wherein said memory control circuits are adapted to operate a direct transfer of data from at least one of said non-volatile memory cells to at least one of said volatile memory cells.

8. A semiconductor device, the device comprising:

a substrate;

a plurality of non-volatile memory cells comprising a first non-volatile memory cell and a second non-volatile memory cell;

each cell comprising;

a channel region;

a source diffusion and a drain diffusion;

wherein said plurality of non-volatile memory cells comprises semiconductor source lines and semiconductor drain lines shared by said first non-volatile memory cell and said second non-volatile memory cell,

wherein one of said semiconductor source lines comprises a source diffusion of said first non-volatile memory cell and said second non-volatile memory cell,

wherein one of said semiconductor drain lines comprises a drain diffusion of said first non-volatile memory cell and said second non-volatile memory cell,

wherein said first non-volatile memory cell and said second non-volatile memory cell also function as volatile floating body memory cells, and

wherein said channel region is electrically isolated from said substrate.

9. The semiconductor device according to claim 8,

wherein at least one of said non-volatile memory cells comprises at least one channel facet,

wherein said at least one channel facet is affected modified by at least two gates,

wherein said at least one channel facet comprises at least two storage locations oriented perpendicular to said at least two gates, and

wherein one of said at least two gates is self-aligned to the other of said at least two gates.

10. The semiconductor device according to claim 8,

wherein at least one of said non-volatile memory cells comprises at least one channel facet,

wherein said at least one channel comprises at least three facets, and

wherein each of said at least three facets has its own charge storage region.

11. The semiconductor device according to claim 8,

wherein at least one of said non-volatile memory cells comprises at least one channel facet, and

wherein said at least one channel facet comprises at least four storage locations.

12. The semiconductor device according to claim 8, further comprising:

a single crystal semiconductor layer overlaying at least a portion of said non-volatile memory cells, and

a plurality of through silicon vias,

wherein said through silicon vias have a radius smaller than 250 nm.

13. The semiconductor device according to claim 8,

wherein each of said non-volatile memory cells comprises at least one channel facet,

wherein said at least one channel facet is modified by at least a first gate and a second gate,

wherein said at least one channel facet comprises at least a first storage location and a second storage location such that said first storage location is substantially closer to said first gate and said second storage location is substantially closer to said second gate, and

wherein said first gate and said second gate are independently controlled by memory control circuits.

14. The semiconductor device according to claim 8, further comprising:

a plurality of volatile memory cells, and

a controller,

wherein said controller is adapted to operate a direct transfer of data from at least one of said non-volatile memory cells to at least one of said volatile memory cells.

15. A semiconductor device, the device comprising:

a plurality of non-volatile memory cells; and

memory control circuits,

wherein at least one of said plurality of non-volatile memory cells comprises at least one channel facet,

wherein said at least one channel facet is affected by at least a first gate and a second gate,

wherein said at least one channel facet comprises at least a first storage location and a second storage location

wherein said first storage location is substantially closer to said first gate and said second storage location is substantially closer to said second gate.

16. The semiconductor device according to claim 15,

wherein one of said first gates is self-aligned to said second gate.

17. The semiconductor device according to claim 15,

wherein said at least one channel facet comprises at least three facets, and

wherein each of said at least three facets has its own charge storage region.

18. The semiconductor device according to claim 15,

wherein said at least one channel facet comprises at least four storage locations.

19. The semiconductor device according to claim 15, further comprising:

a single crystal semiconductor layer overlaying at least a portion of said non-volatile memory cells, and

a plurality of through silicon vias,

wherein said through silicon vias have a radius smaller than 250 nm.

20. The semiconductor device according to claim 15,

wherein said plurality of non-volatile memory cells comprises a first non-volatile memory cell and a second non-volatile memory cell, and

wherein said first non-volatile memory cell and said second non-volatile memory cell also function as volatile floating body memory cells.