Secure erase for data corruption

• US 10,522,229 B2
• Filed: 08/30/2017
• Issued: 12/31/2019
• Est. Priority Date: 08/30/2017
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Luo, Ting, Tanpairoj, Kulachet, Singidi, Harish, Huang, Jianmin, Thomson, Preston, Jean, Sebastien Andre
• Primary Examiner(s): Nguyen, Viet Q
• Application Number:
  US15/691,584
• Publication Number:
  US 20190066799A1
• Time in Patent Office: 853 Days
• Field of Search: 36518533
• CPC Class Codes: G11C 11/5635 Erasing circuits
• CPC Class Codes: G11C 11/5671 using charge trapping in an insulator
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: G11C 16/16 for erasing blocks, e.g. arrays, words, groups
• CPC Class Codes: G11C 16/3409 Circuits or methods to recover overerased nonvolatile memory cells detected during erase verification, usually by means of a "soft" programming step
• CPC Class Codes: G11C 16/3445 Circuits or methods to verify correct erasure of nonvolatile memory cells
• CPC Class Codes: H10B 41/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels

Abstract

Disclosed in some examples are systems, methods, memory devices, and machine readable mediums for a fast secure data destruction for NAND memory devices that renders data in a memory cell unreadable. Instead of going through all the erase phases, the memory device may remove sensitive data by performing only the pre-programming phase of the erase process. Thus, the NAND doesn'"'"'t perform the second and third phases of the erase process. This is much faster and results in data that cannot be reconstructed. In some examples, because the erase pulse is not actually applied and because this is simply a programming operation, data may be rendered unreadable at a per-page level rather than a per-block level as in traditional erases.

Claims

1. A method comprising:

determining, at a memory device, that a value stored in a page of a NAND array of the memory device is to be destroyed; and

in response to the determining, destroying the value in the page without destroying any other data in a block containing the page by applying only a pre-programming pulse to memory cells of the page, the pre-programming pulse bringing a voltage level of the memory cells of the page to a predetermined voltage level.

2. The method of claim 1, comprising:

subsequent to applying the pre-programming pulse;

determining that the page is to be erased; and

responsive to determining that the memory cell is to be erased;

refraining from applying the pre-programming pulse to the memory cells in the page;

applying an erase pulse to the memory cells in the page; and

verifying that the page is erased.

3. The method of claim 1, wherein determining that the value is to be destroyed comprises receiving a command from a host over a communications interface.

4. The method of claim 1, wherein determining that the value stored in the page of the NAND array of the memory device is to be destroyed comprises:

receiving a delete request from a host over a communications interface for a logical block address mapped to the page;

determining that the logical block address is classified as sensitive; and

in response to receiving the delete request and determining that the logical block address is classified as sensitive, determining that the value stored in the page is to be destroyed.

5. The method of claim 4, comprising:

responsive to receiving the delete request, marking the memory cell as unallocated.

14. The method of claim 1, further comprising:

receiving a command identifying a first logical block address of the value;

determining that the page is mapped to the first logical block address and a second logical block address; and

moving a value corresponding to the second logical block address to a new page prior to destroying the value in the memory cell.

6. A memory device comprising:

a NAND memory array;

a memory controller configured to perform operations comprising;

determining that a value stored in a page of the NAND memory array of the memory device is to be destroyed; and

in response to the determining, destroying the value in the page without destroying any other data in a block containing the page by applying only a pre-programming pulse to memory cells of the page, the pre-programming pulse bringing a voltage level of the memory cells of the page to a predetermined voltage level.

7. The memory device of claim 6, wherein the memory controller is further configured to perform operations comprising:

subsequent to applying the pre-programming pulse;

determining that the memory cell is to be erased; and

responsive to determining that the memory cell is to be erased;

refraining from applying the pre-programming pulse to the memory cells in the page;

applying an erase pulse to the memory cells in the page; and

verifying that the page is erased.

8. The memory device of claim 6, wherein the operations of determining that the value is to be destroyed comprises operations of receiving a command from a host over a communications interface.

9. The memory device of claim 6, wherein the operations of determining that the value stored in the page of the NAND array of the memory device is to be destroyed comprises:

receiving a delete request from a host over a communications interface for a logical block address mapped to the page;

determining that the logical block address is classified as sensitive; and

in response to receiving the delete request and determining that the logical block address is classified as sensitive, determining that the value stored in the page of the memory device is to be destroyed.

10. The memory device of claim 9, comprising:

responsive to receiving the delete request, marking the memory cell as unallocated.

15. The memory device of claim 6, wherein the operations further comprise:

receiving a command identifying the value;

determining that the page includes the value and a second value not identified for destruction; and

moving the second value to a new page prior to destroying the value in the memory cell.

11. A non-transitory machine-readable medium, comprising instructions, that when executed by the machine, cause the machine to perform operations comprising:

determining that a value stored in a page of a NAND array a memory device is to be destroyed; and

in response to the determining, destroying the value in the page without destroying any other data in a block containing the page by applying only a pre-programming pulse to memory cells of the page, the pre-programming pulse bringing a voltage level of the memory cells of the page to a predetermined voltage level.

12. The non-transitory machine-readable medium of claim 11,

wherein the operations further comprise:

subsequent to applying the pre-programming pulse;

determining that the memory cell is to be erased; and

responsive to determining that the memory cell is to be erased;

refraining from applying the pre-programming pulse to the memory cells in the page;

applying an erase pulse to the memory cells in the page; and

verifying that the page is erased.

13. The non-transitory machine-readable medium of claim 11, wherein the operations of determining that the value is to be destroyed comprises operations of receiving a command from a host over a communications interface.

16. The non-transitory machine-readable medium of claim 11, wherein the operations further comprise:

receiving a command identifying the value;

determining that the page includes the value and a second value not identified for destruction; and

moving the second value to a new page prior to destroying the value in the memory cell.