Methods and systems for dopant activation using microwave radiation

• US 10,522,356 B2
• Filed: 04/17/2017
• Issued: 12/31/2019
• Est. Priority Date: 08/09/2013
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Tsai, Chun-Hsiung, Yang, Huai-Tei, Yu, Kuo-Feng, Chen, Kei-Wei
• Primary Examiner(s): Eskridge, Cory W
• Application Number:
  US15/488,657
• Publication Number:
  US 20170221713A1
• Time in Patent Office: 988 Days
• CPC Class Codes: H01L 21/02532 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02584 Delta-doping
• CPC Class Codes: H01L 21/02694 Controlling the interface between substrate and epitaxial layer, e.g. by ion implantation followed by annealing
• CPC Class Codes: H01L 21/2252 using predeposition of impurities into the semiconductor surface, e.g. from a gaseous phase
• CPC Class Codes: H01L 21/2254 from or through or into an applied layer, e.g. photoresist, nitrides
• CPC Class Codes: H01L 21/2686 using incoherent radiation
• CPC Class Codes: H01L 21/324 Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering H01L21/20 - H01L21/288 and H01L21/302 - H01L21/322 take precedence
• CPC Class Codes: H01L 21/67115 mainly by radiation
• CPC Class Codes: H01L 21/76895 Local interconnects; Local pads, as exemplified by patent document EP0896365
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/167 further characterised by the doping material H01L29/1604 takes precedence
• CPC Class Codes: H01L 29/32 the imperfections being within the semiconductor body
• CPC Class Codes: H01L 29/45 Ohmic electrodes
• CPC Class Codes: H01L 29/66636 with source or drain recessed by etching or first recessed by etching and then refilled
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7851 with the body tied to the substrate
• CPC Class Codes: H05B 6/80 Apparatus for specific applications stoves or ranges F24C7/02

Abstract

A semiconductor structure includes a substrate, a source/drain (S/D) junction, and an S/D contact. The S/D junction is associated with the substrate and includes a trench-defining wall, a semiconductor layer, and a semiconductor material. The trench-defining wall defines a trench. The semiconductor layer is formed over the trench-defining wall, partially fills the trench, substantially covers the trench-defining wall, and includes germanium. The semiconductor material is formed over the semiconductor layer and includes germanium, a percentage composition of which is greater than a percentage composition of the germanium of the semiconductor layer. The S/D contact is formed over the S/D junction.

Claims

1. A source/drain (S/D) junction of a transistor comprising:

a first silicon-and-germanium-containing layer disposed directly on a substrate;

a second silicon-and-germanium-containing layer disposed directly on the first silicon-and-germanium-containing layer, wherein a percentage composition of germanium of the second silicon-and-germanium-containing layer is greater than a percentage composition of germanium of the first silicon-and-germanium-containing layer; and

wherein the first silicon-and-germanium-containing layer and the second silicon-and-germanium-containing layer are each doped with boron, and further wherein a concentration of boron of the second silicon-and-germanium-containing layer is less than a concentration of boron of the first silicon-and-germanium-containing layer.

2. The S/D junction of claim 1, wherein the concentration of boron of the second silicon-and-germanium-containing layer is about 2E20 atoms/cm³ to about 1E21 atoms/cm³ and the concentration of boron of the first silicon-and-germanium-containing layer is about 1E21 atoms/cm³ to about 3.7E21 atoms/cm³.

3. The S/D junction of claim 1, wherein the percentage composition of germanium of the second silicon-and-germanium-containing layer is between about 50% and about 95% and the percentage composition of germanium of the first silicon-and-germanium-containing layer is between about 35% and about 50%.

4. The S/D junction of claim 1, wherein a percentage composition of germanium of the first silicon-and-germanium-containing layer increases from an outermost portion of the first silicon-and-germanium-containing layer interfacing with the substrate to an innermost portion of the first silicon-and-germanium-containing layer interfacing with the second silicon-and-germanium-containing layer.

5. The S/D junction of claim 4, wherein the concentration of boron of the first silicon-and-germanium-containing layer decreases from the outermost portion of the first silicon-and-germanium-containing layer interfacing with the substrate to the innermost portion of the first silicon-and-germanium-containing layer interfacing with the second silicon-and-germanium-containing layer.

6. A semiconductor structure comprising:

a source/drain (S/D) junction associated with a substrate and including;

a source/drain semiconductor layer disposed directly on the substrate, wherein the source/drain semiconductor layer includes a first concentration of boron, and

a source/drain semiconductor material that includes a second concentration of boron disposed directly on the source/drain semiconductor layer, wherein the second concentration of boron is less than the first concentration of boron; and

a S/D contact disposed over the S/D junction.

7. The semiconductor structure of claim 6, wherein the source/drain semiconductor layer further includes a first percentage composition of germanium and the source/drain semiconductor material further includes a second percentage composition of germanium, wherein the second percentage composition of germanium is greater than the first percentage composition of germanium.

8. The semiconductor structure of claim 6, wherein the source/drain semiconductor material includes an upper layer and a lower layer, wherein the lower layer is disposed between the source/drain semiconductor layer and the upper layer, and further wherein the lower layer includes the second concentration of boron and the upper layer includes a third concentration of boron that is greater than the second concentration of boron.

9. The semiconductor structure of claim 8, wherein a thickness of the upper layer from a top surface of the S/D junction to the lower layer is about 5 nm to about 15 nm.

10. The semiconductor structure of claim 6, wherein the first concentration of boron of the source/drain semiconductor layer decreases from an interface of the source/drain semiconductor layer with the substrate to an interface of the source/drain semiconductor layer with the source/drain semiconductor material.

11. The semiconductor structure of claim 6, wherein the substrate includes silicon, the source/drain semiconductor layer includes silicon and germanium, and the source/drain semiconductor material includes silicon and germanium.

12. The semiconductor structure of claim 6, wherein the substrate is a fin of fin-like field effect transistor.

13. A method of forming a source/drain junction comprising:

forming a first silicon-and-germanium-containing layer directly on a substrate, wherein the first silicon-and-germanium-containing layer includes a first percentage composition of germanium;

forming a second silicon-and-germanium-containing layer directly on the first silicon-and-germanium-containing layer, wherein the second silicon-and-germanium-containing layer includes a second percentage composition of germanium that is greater than the first percentage composition of germanium;

doping the first silicon-and-germanium-containing layer and the second silicon-and-germanium-containing layer with boron, wherein a boron concentration of the second silicon-and-germanium-containing layer is less than a boron concentration of the first silicon-and-germanium-containing layer; and

forming a S/D contact over the second silicon-and-germanium-containing layer.

14. The method of forming a S/D junction of claim 13, further comprising:

forming microwave-absorption material on the S/D junction;

applying microwave radiation to the microwave-absorption material; and

etchably removing the microwave-absorption material.

15. The method of forming a S/D junction of claim 13, wherein a boron concentration of an upper layer of the second silicon-and-germanium-containing layer is greater than a boron concentration of a lower layer of the second silicon-and-germanium-containing layer.

16. The method of forming a S/D junction of claim 13, wherein forming the first silicon-and-germanium-containing layer includes:

forming an innermost sublayer having a first percentage composition of germanium, wherein the innermost sublayer interfaces with the second silicon-and-germanium-containing layer; and

forming an outermost sublayer having a second percentage composition of germanium that is less than the first percentage composition of germanium, wherein the outermost sublayer interfaces with the substrate.

17. The method of forming a S/D junction of claim 16, wherein a boron concentration of the outermost sublayer is greater than a boron concentration of the innermost sublayer.

18. The method of forming a S/D junction of claim 13, wherein the first percentage composition of germanium is between about 35% and about 50% and the second percentage composition of germanium is between about 50% and about 95%.

19. The method of forming a S/D junction of claim 13, wherein the substrate is a fin of a fin-like field effect transistor.

20. The method of forming an S/D junction of claim 13, wherein the second percentage composition of germanium of the second silicon-and-germanium-containing layer increases from a bottom surface of the second silicon-and-germanium-containing layer that interfaces with the first silicon-and-germanium-containing layer to a top surface of the second silicon-and-germanium-containing layer.