Semiconductor device and manufacturing method thereof

• US 10,522,368 B2
• Filed: 07/30/2018
• Issued: 12/31/2019
• Est. Priority Date: 02/18/2016
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Chao, Yuan-Shun, Kuo, Chih-Wei
• Primary Examiner(s): Assouman, Herve-Louis Y
• Application Number:
  US16/049,138
• Publication Number:
  US 20180350625A1
• Time in Patent Office: 519 Days
• Field of Search: None
• CPC Class Codes: H01L 2029/7858 having contacts specially adapted to the FinFET geometry, e.g. wrap-around contacts
• CPC Class Codes: H01L 21/28518 the conductive layers comprising silicides H01L21/28537 takes precedence
• CPC Class Codes: H01L 21/44 Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/38 - H01L21/428
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/26 including, apart from doping materials or other impurities, elements provided for in two or more of the groups H01L29/16, H01L29/18, H01L29/20, H01L29/22, H01L29/24 , e.g. alloys
• CPC Class Codes: H01L 29/41791 for transistors with a horizontal current flow in a vertical sidewall, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/45 Ohmic electrodes
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/66969 of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

A semiconductor device includes an isolation insulating layer disposed over a substrate, a fin structure disposed over the substrate, and extending in a first direction in plan view, an upper portion of the fin structure being exposed from the isolation insulating layer, a gate structure disposed over a part of the fin structure, the gate structure extending in a second direction crossing the first direction, and a source/drain structure formed on the upper portion of the fin structure, which is not covered by the gate structure and exposed from the isolation insulating layer. The source/drain structure includes a SiP layer, and an upper portion of the source/drain structure includes an alloy layer of Si, Ge and Ti.

Claims

1. A semiconductor device, comprising:

an isolation insulating layer disposed over a substrate;

a fin structure disposed over the substrate, and extending in a first direction in plan view, an upper portion of the fin structure being exposed from the isolation insulating layer;

a gate structure disposed over a part of the fin structure, the gate structure extending in a second direction crossing the first direction; and

a source/drain structure formed on the upper portion of the fin structure, which is not covered by the gate structure and exposed from the isolation insulating layer, wherein;

the semiconductor device is an n-channel semiconductor field effect transistor,

the source/drain structure includes a SiP layer, and

an upper portion of the source/drain structure includes an alloy layer of Si, Ge and Ti.

2. The semiconductor device of claim 1, wherein an amount of phosphorous in the SiP layer is in a range from 1×

10²⁰ cm<sup>−

3</sup> to 5×

10²¹ cm<sup>−

3</sup>.

3. The semiconductor device of claim 1, wherein the alloy layer is in contact with the SiP layer.

4. The semiconductor device of claim 1, wherein the SiP layer includes a first SiP layer and a second SiP layer having different phosphorous concentration from each other.

5. The semiconductor device of claim 4, wherein an amount of phosphorous in the first SiP layer is smaller than an amount of phosphorous in the second SiP layer.

6. The semiconductor device of claim 5, wherein the amount of phosphorous in the first SiP layer is in a range from 2×

10²⁰ cm<sup>−

3</sup> to 7×

10²⁰ cm<sup>−

3</sup>, and the amount of phosphorous in the second SiP layer is in a range from 3×

10²⁰ cm<sup>−

3</sup> to 4×

10²¹ cm<sup>−

3</sup>.

7. A semiconductor device including an n-type FET, the n-type FET comprising:

an isolation insulating layer disposed over a substrate;

a fin structure disposed over the substrate, and extending in a first direction in plan view, an upper portion of the fin structure being exposed from the isolation insulating layer; and

a source/drain structure formed on the upper portion of the fin structure, wherein;

the source/drain structure includes a SiP layer and a SiGe layer disposed over the SiP layer and an alloy layer of Si, Ge and Ti disposed over the SiGe layer.

8. The semiconductor device of claim 7, wherein the SiP layer includes a first SiP layer and a second SiP layer having different phosphorous concentration from each other.

9. The semiconductor device of claim 8, wherein an amount of phosphorous in the first SiP layer is smaller than an amount of phosphorous in the second SiP layer.

10. The semiconductor device of claim 9, wherein the amount of phosphorous in the first SiP layer is in a range from 2×

10²⁰ cm<sup>−

3</sup> to 7×

10²⁰ cm<sup>−

3</sup>, and the amount of phosphorous in the second SiP layer is in a range from 3×

10²⁰ cm<sup>−

3</sup> to 4×

10²¹ cm<sup>−

3</sup>.

11. The semiconductor device of claim 7, wherein the SiGe layer is a Si_1-xGe_x layer, where x is in a range from 0.25 to 0.5.

12. The semiconductor device of claim 11, wherein the SiGe layer further contains phosphorous.

13. The semiconductor device of claim 12, wherein an amount of phosphorus in the Si_1-xGe_x layer is in a range from 1×

10²⁰ cm<sup>−

3</sup> to 5×

10²¹ cm<sup>−

3</sup>.

14. A semiconductor device including an n-type FET, the n-type FET comprising:

an isolation insulating layer disposed over a substrate;

a fin structure disposed over the substrate, and extending in a first direction in plan view, an upper portion of the fin structure being exposed from the isolation insulating layer;

a source/drain structure formed on the upper portion of the fin structure; and

a source/drain contact disposed over the source/drain structure, wherein;

the source/drain structure includes a SiP layer,

a layer containing Si and Ge is formed over the SiP layer,

an upper part of the layer is an alloy layer of Si, Ge and Ti and is in contact with the source/drain contact, and

a lower part of the layer containing Si and Ge not in contact with the source/drain contact is a Si_1-xGe_x layer without Ti.

15. The semiconductor device of claim 14, wherein the SiP layer includes a first SiP layer and a second SiP layer having different phosphorous concentration from each other.

16. The semiconductor device of claim 15, wherein an amount of phosphorous in the first SiP layer is smaller than an amount of phosphorous in the second SiP layer.

17. The semiconductor device of claim 14, wherein the amount of phosphorous in the first SiP layer is in a range from 2×

10²⁰ cm<sup>−

3</sup> to 7×

10²⁰ cm<sup>−

3</sup>, and the amount of phosphorous in the second SiP layer is in a range from 3×

10²⁰ cm<sup>−

3</sup> to 4×

10²¹ cm<sup>−

3</sup>.

18. The semiconductor device of claim 14, wherein x in the Si_1-xGe_x layer is in a range from 0.25 to 0.5.

19. The semiconductor device of claim 14, wherein the Si_1-xGe_x layer further contains phosphorous, and an amount of phosphorus in the Si _1-xGe_x layer is in a range from 1×

10²⁰ cm<sup>−

3</sup> to 5×

10²¹ cm<sup>−

3</sup>.