Method and structure for FinFET isolation

• US 10,522,414 B2
• Filed: 12/17/2018
• Issued: 12/31/2019
• Est. Priority Date: 10/17/2014
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Chang, Che-Cheng, Lin, Chih-Han, Lin, Jr-Jung
• Primary Examiner(s): Ho, Anthony
• Application Number:
  US16/222,837
• Publication Number:
  US 20190122934A1
• Time in Patent Office: 379 Days
• CPC Class Codes: H01L 21/823431 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823468 with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
• CPC Class Codes: H01L 21/823481 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 27/0886 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

A method of forming a semiconductor device includes receiving a substrate having a fin extending from the substrate, first and second dummy gate stacks over the substrate and engaging the fin; removing the first and second dummy gate stacks thereby forming a first trench and a second trench, wherein the first and second trenches expose first and second portions of the fin respectively; removing the first portion of the fin; and forming a gate stack in the second trench, the gate stack engaging the second portion of the fin.

Claims

1. A method of forming a semiconductor device, comprising:

receiving a substrate having a fin extending from the substrate, first and second dummy gate stacks over the substrate and engaging the fin;

removing the first and second dummy gate stacks thereby forming a first trench and a second trench, wherein the first and second trenches expose first and second portions of the fin respectively;

removing the first portion of the fin; and

forming a gate stack in the second trench, the gate stack engaging the second portion of the fin.

2. The method of claim 1, further comprising:

filling the first trench with a dielectric material.

3. The method of claim 1, wherein sidewalls of the first and second dummy gate stacks are covered by spacer features.

4. The method of claim 1, wherein the first and second dummy gate stacks are over a first surface of an isolation structure over the substrate, and the removing of the first portion of the fin includes:

expanding the first trench below the first surface.

5. The method of claim 1, wherein the removing of the first portion of the fin includes:

forming a masking element over the second portion of the fin; and

performing an etching process to the first portion of the fin.

6. The method of claim 1, further comprising, after the removing of the first portion of the fin:

performing an ashing process to the first trench so as to recess the fin along its length.

7. The method of claim 6, wherein:

sidewalls of the first and second dummy gate stacks are covered by spacer features having a first thickness; and

the ashing process recesses the fin by a distance less than the first thickness.

8. The method of claim 6, wherein the ashing process exposes a first surface of the fin, further comprising:

forming a dielectric layer over the first surface.

9. The method of claim 8, wherein the dielectric layer includes one of:

silicon oxide and silicon nitride.

10. The method of claim 1, wherein the gate stack includes a high-k dielectric layer and a work function metal layer.

11. A method of forming a semiconductor device, comprising:

receiving a substrate having an active fin, an isolation structure over the substrate, a plurality of dummy gate stacks over a first surface of the isolation structure and engaging the active fin;

removing the dummy gate stacks thereby forming first, second, and third trenches, wherein the second trench is between the first and third trenches, and the first, second, and third trenches expose first, second, and third portions of the active fin respectively;

removing the second portion of the active fin; and

forming gate stacks in the first and third trenches, the gate stacks engaging the first and third portions of the active fin.

12. The method of claim 11, wherein the removing of the second portion of the active fin includes:

forming a masking element covering the first and third portions of the active fin; and

etching the second portion of the active fin below the first surface.

13. The method of claim 12, further comprising:

performing an ashing process to both remove the masking element and to recess the active fin through the second trench.

14. The method of claim 11, further comprising, after the removing of the second portion of the active fin:

performing one of oxidation and nitridation processes to surfaces of the active fin that are exposed through the second trench.

15. The method of claim 11, further comprising:

filling the second trench with a dielectric material.

16. A method of forming a semiconductor device, comprising:

receiving a substrate having first and second fins extending lengthwise generally along a same line, wherein each of the first and second fins has first and second ends, and the second end of the first fin is adjacent to the first end of the second fin;

forming a first gate stack over the substrate and engaging the first fin;

forming a second gate stack over the substrate and engaging the second fin;

forming a first isolation structure over the first end of the first fin;

forming a second isolation structure over the second end of the second fin; and

forming a third isolation structure adjacent to both the second end of the first fin and the first end of the second fin.

17. The method of claim 16, wherein each of the first, second, and third isolation structures is surrounded by respective spacer features.

18. The method of claim 16, further comprising:

forming a fourth isolation structure over the substrate, wherein the first and second gate stacks are formed over the fourth isolation structure.

19. The method of claim 18, wherein:

the first and second gate stacks are formed over a first surface of the fourth isolation structure; and

the third isolation structure is formed over a second surface of the fourth isolation structure, wherein the second surface is lower than the first surface.

20. The method of claim 16, wherein the second end of the first fin and the first end of the second fin each include a dielectric material layer abutting the third isolation structure.