Package structure and method of fabricating the same

• US 10,522,470 B1
• Filed: 07/15/2018
• Issued: 12/31/2019
• Est. Priority Date: 07/15/2018
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Chang, Jung-Hua, Kao, Chin-Fu
• Primary Examiner(s): Ullah, Elias
• Application Number:
  US16/035,693
• Publication Number:
  US 20200020633A1
• Time in Patent Office: 534 Days
• CPC Class Codes: H01L 21/565 Moulds
• CPC Class Codes: H01L 21/568 Temporary substrate used as encapsulation process aid H01L21/4832 and H01L21/566 take precedence
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 21/6836 Wafer tapes, e.g. grinding or dicing support tapes adhesive tapes in general C09J7/20
• CPC Class Codes: H01L 21/76876 for deposition from the gas phase, e.g. CVD
• CPC Class Codes: H01L 2221/68327 used during dicing or grinding
• CPC Class Codes: H01L 2221/68331 of passive members, e.g. die mounting substrate
• CPC Class Codes: H01L 2221/6834 used to protect an active side of a device or wafer
• CPC Class Codes: H01L 2221/68345 used as a support during the manufacture of self supporting substrates
• CPC Class Codes: H01L 2221/68359 used as a support during manufacture of interconnect decals or build up layers
• CPC Class Codes: H01L 2221/68372 used to support a device or wafer when forming electrical connections thereto
• CPC Class Codes: H01L 2224/0231 Manufacturing methods of the redistribution layers
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/18 High density interconnect [HDI] connectors; Manufacturing methods related thereto
• CPC Class Codes: H01L 2224/19 Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 2224/96 the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
• CPC Class Codes: H01L 23/3128 the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/49816 Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 23/5384 Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors H01L23/5383, H01L23/5385 take precedence; pins attached to insulating substrates H01L23/49811
• CPC Class Codes: H01L 23/5389 : the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 24/17 : of a plurality of bump connectors
• CPC Class Codes: H01L 24/19 : Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 24/20 : Structure, shape, material or disposition of high density interconnect preforms

Abstract

A package structure including a first semiconductor die, a second semiconductor die, a molding compound, an interconnect structure, first conductive features, through insulator vias, an insulating encapsulant and a redistribution layer is provided. The molding compound is encapsulating the first semiconductor die and the second semiconductor die. The interconnect structure is disposed on the molding compound and electrically connecting the first semiconductor die to the second semiconductor die. The first conductive features are electrically connected to the first semiconductor die and the second semiconductor die, wherein each of the first conductive features has a recessed portion. The through insulator vias are disposed on the recessed portion of the first conductive features and electrically connected to the first and second semiconductor die. The insulating encapsulant is encapsulating the interconnect structure and the through insulator vias. The redistribution layer is disposed on the insulating encapsulant and over the interconnect structure.

Claims

1. A package structure, comprising:

a first semiconductor die;

a second semiconductor die disposed adjacent to the first semiconductor die;

a molding compound encapsulating the first semiconductor die and the second semiconductor die;

an interconnect structure disposed on the molding compound and electrically connecting the first semiconductor die to the second semiconductor die;

a plurality of first conductive features disposed on the molding compound and electrically connected to the first semiconductor die and the second semiconductor die, wherein each of the first conductive features has a recessed portion,

a plurality of through insulator vias disposed on the recessed portion of the plurality of first conductive features and electrically connected to the first semiconductor die and the second semiconductor die, wherein the plurality of through insulator vias surrounds the interconnect structure;

an insulating encapsulant encapsulating the interconnect structure and the plurality of through insulator vias, and separating the interconnection structure from the plurality of through insulator vias; and

a redistribution layer disposed on the insulating encapsulant and over the interconnect structure, wherein the redistribution layer is electrically connected to the plurality of through insulator vias.

2. The package structure according to claim 1, further comprising a plurality of second conductive features disposed on the molding compound and electrically connected to the first semiconductor die and the second semiconductor die, wherein the plurality of second conductive features electrically connects the first semiconductor die and the second semiconductor die to the interconnect structure.

3. The package structure according to claim 2, wherein a width of the plurality of second conductive features is smaller than a width of the plurality of first conductive features.

4. The package structure according to claim 3, wherein the width of the plurality of first conductive features is in a range of 25 μ

m to 60 μ

m, and the width of the plurality of second conductive features is in a range of 10 μ

m to 20 μ

m.

5. The package structure according to claim 1, wherein a depth of the recessed portion of the plurality of first conductive features is in a range of 2 μ

m to 10 μ

m.

6. The package structure according to claim 1, further comprising a plurality of seed layers disposed in between the recessed portion of the plurality of first conductive features and the plurality of through insulator vias.

7. A package structure, comprising:

a first semiconductor die having a plurality of conductive vias;

a second semiconductor die disposed adjacent to the first semiconductor die and having a plurality of conductive vias;

a molding compound encapsulating the first semiconductor die and the second semiconductor die;

a plurality of first conductive features disposed on the molding compound and physically connected to the plurality of conductive vias of the first semiconductor die and the plurality of conductive vias of the second semiconductor die, wherein each of the first conductive features comprises flank portions and a recessed portion joining the flank portions;

a plurality of second conductive features disposed adjacent to the plurality of first conductive features and on the molding compound and physically connected to the plurality of conductive vias of the first semiconductor die and the plurality of conductive vias of the second semiconductor die;

an interconnect structure disposed on the plurality of second conductive features and electrically connecting the first semiconductor die to the second semiconductor die;

a plurality of through insulator vias disposed on the recessed portion of the plurality of first conductive features and electrically connected to the first semiconductor die and the second semiconductor die, wherein the plurality of through insulator vias surrounds the interconnect structure;

an insulating encapsulant encapsulating the interconnect structure and the plurality of through insulator vias, and separating the interconnection structure from the plurality of through insulator vias; and

a redistribution layer disposed on the insulating encapsulant and over the interconnect structure, wherein the redistribution layer is electrically connected to the plurality of through insulator vias.

8. The package structure according to claim 7, wherein a level of a top surface of the flank portions is higher than a level of a top surface of the recessed portions in the first conductive features.

9. The package structure according to claim 8, wherein the top surface of the flank portions of the first conductive features is coplanar with a top surface of the second conductive features.

10. The package structure according to claim 7, wherein a width of the plurality of second conductive features is smaller than a width of the plurality of first conductive features.

11. The package structure according to claim 10, wherein the width of the plurality of first conductive features is in a range of 25 μ

m to 60 μ

m, and the width of the plurality of second conductive features is in a range of 10 μ

m to 20 μ

m.

12. The package structure according to claim 7, wherein a depth of the recessed portion of the plurality of first conductive features is in a range of 2 μ

m to 10 μ

m.

13. The package structure according to claim 7, further comprising a plurality of seed layers disposed in between the recessed portion of the plurality of first conductive features and the plurality of through insulator vias.

14. The package structure according to claim 7, wherein the plurality of through insulator vias is connected to the recessed portion, and physically separated from the flank portions of the plurality of first conductive features.

15. A method of fabricating a package structure, comprising:

providing a carrier;

disposing a first semiconductor die having a plurality of conductive vias on the carrier;

disposing a second semiconductor die having a plurality of conductive vias on the carrier adjacent to the first semiconductor die;

forming a molding compound encapsulating the first semiconductor die and the second semiconductor die;

forming a dielectric layer on the molding compound and patterning the dielectric layer to form a plurality of first openings and a plurality of second openings, wherein the plurality of first openings surround the plurality of second openings, and a width of the plurality of first openings is greater than a width of the plurality of second openings;

forming a plurality of first conductive features in the plurality of first openings, wherein the plurality of first conductive features is formed with flank portions and a recessed portion joining the flank portions, and the recessed portion being physically connected to the plurality of conductive vias of the first semiconductor die and the plurality of conductive vias of the second semiconductor die;

forming a plurality of second conductive features in the plurality of second openings, wherein the plurality of second conductive features is physically connected to the plurality of conductive vias of the first semiconductor die and the plurality of conductive vias of the second semiconductor die;

forming a plurality of through insulator vias on the recessed portion of the plurality of first conductive features, the plurality of through insulator vias being electrically connected to the first semiconductor die and the second semiconductor die;

disposing an interconnect structure on the plurality of second conductive features and electrically connecting the first semiconductor die to the second semiconductor die;

forming an insulating encapsulant encapsulating the interconnect structure and the plurality of through insulator via, wherein the insulating encapsulant is separating the interconnection structure from the plurality of through insulator vias;

forming a redistribution layer on the insulating encapsulant and over the interconnect structure, wherein the redistribution layer is electrically connected to the plurality of through insulator vias; and

de-bonding the carrier.

16. The method of fabricating the package structure according to claim 15, wherein the width of the first openings is smaller than 50 μ

m and the width of the second openings is smaller than 15 μ

m.

17. The method of fabricating the package structure according to claim 15, wherein the plurality of through insulator vias is formed by the following steps:

forming a seed layer on the dielectric layer and over the first conductive features and the second conductive features;

providing a photoresist pattern on the seed layer covering the plurality of second conductive features and the flank portions of the plurality of first conductive features, wherein the photoresist pattern has openings exposing portions of the seed layer located above the recessed portions;

forming a metallic material on the exposed portions of the seed layer to form the plurality of through insulator vias; and

removing the photoresist pattern and portions of the seed layer exposed by the through insulator vias.

18. The method of fabricating the package structure according to claim 15, wherein a width of the plurality of first conductive features is in a range of 25 μ

m to 60 μ

m, and a width of the plurality of second conductive features is in a range of 10 μ

m to 20 μ

m.

19. The method of fabricating the package structure according to claim 15, wherein a depth of the recessed portion of the plurality of first conductive features is in a range of 2 μ

m to 10 μ

m.

20. The method of fabricating the package structure according to claim 15, wherein a level of a top surface of the flank portions is higher than a level of a top surface of the recessed portions in the first conductive features.