Method of making package assembly including stress relief structures

• US 10,522,477 B2
• Filed: 11/13/2017
• Issued: 12/31/2019
• Est. Priority Date: 11/09/2012
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Chen, Hsien-Wei
• Primary Examiner(s): Williams, Alexander O
• Application Number:
  US15/810,602
• Publication Number:
  US 20180068960A1
• Time in Patent Office: 778 Days
• Field of Search: 257723, 257685, 257778, 257777, 257686
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 23/16 Fillings or auxiliary members in containers or encapsulations, e.g. centering rings H01L23/42, H01L23/552 take precedence
• CPC Class Codes: H01L 23/5384 Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors H01L23/5383, H01L23/5385 take precedence; pins attached to insulating substrates H01L23/49811
• CPC Class Codes: H01L 23/562 Protection against mechanical damage H01L23/02, H01L23/28 take precedence
• CPC Class Codes: H01L 25/0655 the devices being arranged next to each other
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/3511 Warping

Abstract

A method of making a semiconductor package structure includes bonding a plurality of dies to a substrate, wherein a first die of the plurality of dies is larger than a second die of the plurality of dies. The method further includes adhering a first stress relief structure to the substrate at a corner of the substrate, wherein a distance between the first stress relief structure to a closest die of the plurality of dies to the first stress relief structure is a first distance. The method further includes adhering a second stress relief structure to the substrate along a single edge of the substrate, wherein a distance between the second stress relief structure to a closest die of the plurality of dies to the second stress relief structure is the first distance.

Claims

1. A method of making a semiconductor package structure comprising:

bonding a plurality of dies to a substrate, wherein a first die of the plurality of dies is larger than a second die of the plurality of dies;

adhering a first stress relief structure to the substrate at a corner of the substrate, wherein a distance between the first stress relief structure to a closest die of the plurality of dies to the first stress relief structure is a first distance; and

adhering a second stress relief structure to the substrate along a single edge of the substrate, wherein a distance between the second stress relief structure to a closest die of the plurality of dies to the second stress relief structure is the first distance.

2. The method of claim 1, wherein the adhering of the first stress relief structure comprises adhering the first stress relief structure to the substrate using an epoxy, urethane, polyurethane, or silicone elastomers.

3. The method of claim 1, wherein the adhering of the first stress relief structure comprises curing an adhesive used to adhere the first stress relief structure to the substrate.

4. The method of claim 1, wherein the adhering of the first stress relief structure comprises adhering the first stress relief structure to the substrate using an adhesive having a thermal conductivity greater than about 10 W/m°

C.

5. The method of claim 1, wherein the adhering of the first stress relief structure to the substrate comprises adhering the first stress relief structure at a location to establish the first distance greater than about 2 microns (μ

m).

6. The method of claim 1, wherein the adhering of the second stress relief structure to the substrate comprises adhering the second stress relief structure comprising a same material as the first stress relief structure.

7. The method of claim 1, wherein the adhering of the second stress relief structure to the substrate comprises adhering the second stress relief structure comprising a plurality of discontinuous segments.

8. The method of claim 1, wherein the adhering of the first stress relief structure comprises adhering the first stress relief structure having an L-shape.

9. The method of claim 1, wherein the adhering of the first stress relief structure to the substrate comprises coating an adhesive material on the substrate.

10. A method of making a semiconductor package structure comprising:

bonding a plurality of dies to a substrate, wherein a first die of the plurality of dies is larger than a second die of the plurality of dies;

depositing a stress relief material on the substrate;

patterning the stress relief material to define a first stress relief structure to the substrate at a corner of the substrate and a second stress relief structure along a single edge of the substrate, wherein a distance between the first stress relief structure to a closest die of the plurality of dies to the first stress relief structure is a first distance, and a distance between the second stress relief structure to a closest die of the plurality of dies to the second stress relief structure is the first distance.

11. The method of claim 10, wherein the patterning of the stress relief material comprises a photolithography process.

12. The method of claim 10, wherein the patterning of the stress relief material comprises an etching process.

13. The method of claim 10, wherein the depositing of the stress relief material comprises depositing the stress relief material having a thermal conductivity greater than about 20 W/m°

C.

14. The method of claim 10, wherein the patterning of the stress relief material comprises defining the second stress relief structure comprising a plurality of discontinuous segments.

15. The method of claim 10, wherein the patterning of the stress relief material comprises defining the first stress relief structure comprising an L-shape.

16. A method of making a semiconductor package structure comprising:

bonding a plurality of dies to a substrate, wherein a first die of the plurality of dies is larger than a second die of the plurality of dies;

defining a first stress relief structure on the substrate, wherein a distance between the first stress relief structure to a closest die of the plurality of dies to the first stress relief structure is a first distance; and

defining a second stress relief structure on the substrate, wherein a distance between the second stress relief structure to a closest die of the plurality of dies to the second stress relief structure is the first distance, and the second stress relief structure is discontinuous with respect to the first stress relief structure.

17. The method of claim 16, wherein the defining of the first stress relief structure comprises:

depositing a stress relief material on the substrate; and

patterning the stress relief material.

18. The method of claim 16, wherein the defining of the first stress relief structure comprises adhering the first stress relief structure to the substrate.

19. The method of claim 16, wherein the defining of the first stress relief structure comprises:

defining the first stress relief structure adjacent to a corner of at least one die of the plurality of dies, wherein the first stress relief structure comprises a first portion extending along a first side of the at least one die and a second portion extending along a second side of the at least one die, and the first portion is continuous with the second portion.

20. The method of claim 16, wherein the defining of the second stress relief structure comprises defining the second stress relief structure along a single edge of the substrate.