Post-passivation interconnect structure

• US 10,522,481 B2
• Filed: 11/05/2018
• Issued: 12/31/2019
• Est. Priority Date: 12/07/2011
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Chen, Hsien-Wei, Tsai, Hao-Yi, Lii, Mirng-Ji, Yu, Chen-Hua
• Primary Examiner(s): Le, Thao X
• Assistant Examiner(s): Ida, Geoffrey H
• Application Number:
  US16/181,130
• Publication Number:
  US 20190074255A1
• Time in Patent Office: 421 Days
• CPC Class Codes: H01L 2224/02235 Reinforcing structures
• CPC Class Codes: H01L 2224/02255 Shape of the auxiliary member
• CPC Class Codes: H01L 2224/02375 Top view
• CPC Class Codes: H01L 2224/02377 Fan-in arrangement
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05008 Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body, e.g.
• CPC Class Codes: H01L 2224/05022 the internal layer being at least partially embedded in the surface
• CPC Class Codes: H01L 2224/05027 the internal layer extending out of an opening
• CPC Class Codes: H01L 2224/05124 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05166 Titanium [Ti] as principal constituent
• CPC Class Codes: H01L 2224/05181 Tantalum [Ta] as principal constituent
• CPC Class Codes: H01L 2224/05186 with a principal constituent of the material being a non metallic, non metalloid inorganic material
• CPC Class Codes: H01L 2224/05552 in top view
• CPC Class Codes: H01L 2224/05569 the external layer being disposed on a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05572 the external layer extending out of an opening
• CPC Class Codes: H01L 2224/05647 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05655 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/13022 the bump connector being at least partially embedded in the surface
• CPC Class Codes: H01L 2224/13024 the bump connector being disposed on a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/13111 : Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/13113 : Bismuth [Bi] as principal constituent
• CPC Class Codes: H01L 2224/13116 : Lead [Pb] as principal constituent
• CPC Class Codes: H01L 2224/13139 : Silver [Ag] as principal constituent
• CPC Class Codes: H01L 2224/13147 : Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/13155 : Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 23/3114 : the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 23/3192 : Multilayer coating
• CPC Class Codes: H01L 23/522 : including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
• CPC Class Codes: H01L 23/525 : with adaptable interconnections
• CPC Class Codes: H01L 23/562 : Protection against mechanical damage H01L23/02, H01L23/28 take precedence
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01024 : Chromium [Cr]
• CPC Class Codes: H01L 2924/01028 : Nickel [Ni]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/04941 : TiN
• CPC Class Codes: H01L 2924/04953 : TaN
• CPC Class Codes: H01L 2924/12042 : LASER

Abstract

A semiconductor device includes a semiconductor substrate, a passivation layer overlying the semiconductor substrate, and an interconnect structure overlying the passivation layer. The interconnect structure includes a landing pad region and a dummy region electrically separated from each other. A protective layer is formed on the interconnect structure and has a first opening exposing a portion of the landing pad region and a second opening exposing a portion of the dummy region. A metal layer is formed on the exposed portion of landing pad region and the exposed portion of the dummy region. A bump is formed on the metal layer overlying the landing pad region.

Claims

1. A semiconductor device, comprising:

a semiconductor substrate comprising circuitry and a plurality of metal layers formed between dielectric layers operable to route electrical signals formed therein;

a passivation layer overlying the semiconductor substrate;

an interconnect structure overlying and interfacing a top surface of the passivation layer, the interconnect structure comprising a landing pad conductive element and a plurality of dummy conductive elements, wherein the landing pad conductive element and the plurality of dummy conductive elements are electrically separated;

a protective layer overlying the interconnect structure and comprising a first opening exposing a portion of the landing pad conductive element and a second opening exposing a portion of each of the plurality of dummy conductive elements;

a metal layer comprising a first portion on a topmost surface of the protective layer and on the exposed portion of the landing pad conductive element and a plurality of second portions on the topmost surface of the protective layer and on the exposed portion of each of the plurality of dummy conductive elements, the plurality of second portions of the metal layer being electrically separated from the semiconductor substrate and from the first portion of the metal layer; and

a single bump on the first portion of the metal layer overlying the landing pad conductive element;

wherein each of the plurality of dummy conductive elements adjoins with a respective one of the plurality of second portions of the metal layer to from a plurality of pillars, the plurality of pillars surrounding the single bump in a plan view, and wherein an only bump surrounded by the plurality of pillars is the single bump.

2. The semiconductor device of claim 1, wherein the interconnect structure further includes an interconnect line region coupled to the landing pad conductive element.

3. The semiconductor device of claim 2, wherein the interconnect line region traverses between a first pillar and a second pillar of the plurality of pillars in the plan view.

4. The semiconductor device of claim 1, wherein the metal layer comprises at least one of a titanium layer, a copper layer, or a nickel layer.

5. The semiconductor device of claim 1, wherein the landing pad conductive element and the plurality of dummy conductive elements of the interconnect structure includes a copper layer.

6. The semiconductor device of claim 1, wherein the protective layer comprises a plurality of second openings adjacent to the first opening, and the plurality of second portions of the metal layer fills the plurality of second openings.

7. The semiconductor device of claim 1, wherein the protective layer includes a polymer.

8. The semiconductor device of claim 1, further comprising a conductive pad formed on the semiconductor substrate, wherein the conductive pad is partially covered by the passivation layer, and the conductive pad is electrically connected to the landing pad conductive element of the interconnect structure and the conductive pad has a direct interface with a surface of the landing pad conductive element.

9. The semiconductor device of claim 1, wherein each of the plurality of pillars is a square shape.

10. The semiconductor device of claim 9, wherein each of the plurality of pillars has with a length of at least 5 μ

m, the length measured in the plan view.

11. The semiconductor device of claim 1, wherein each of the plurality of pillars is spaced from an adjacent one of the plurality of pillars by at least 5 μ

m.

12. The semiconductor device of claim 11, wherein a distance between one of the plurality of pillars and the first portion of the metal layer is greater than 10 μ

m.

13. A semiconductor device, comprising:

a semiconductor substrate comprising circuitry and a plurality of inter-metal dielectric (IMD) layers and associated metal layers formed therein;

a post-passivation interconnect (PPI) structure having an interconnect line region, a landing pad region and a plurality of dummy regions, wherein the interconnect line region and the landing pad region are contiguous conductive material and each of the plurality of dummy regions is electrically separated from the interconnect line region and the landing pad region;

an under-bump-metallization (UBM) layer formed on the landing pad region;

a metal layer formed on each of the plurality of dummy regions of the PPI structure to form a plurality of metal pillars each electrically separated from one another; and

a single bump on the UBM layer, wherein the plurality of metal pillars each being spaced a same distance from the single bump.

14. The semiconductor device of claim 13, wherein the plurality of metal pillars surrounds the single bump in a plan view.

15. The semiconductor device of claim 13, wherein the metal layer comprises at least one of a titanium layer, a copper layer, or a nickel layer.

16. The semiconductor device of claim 13, further comprising a polymer layer over the interconnect line region.

17. The semiconductor device of claim 16, wherein the metal pillars extend through the polymer layer.

18. A semiconductor device, comprising:

a semiconductor substrate comprising circuitry and a plurality of metal layers formed between dielectric layers operable to route electrical signals formed therein;

a passivation layer overlying the semiconductor substrate;

an interconnect structure overlying and interfacing a top surface of the passivation layer, the interconnect structure comprising a first landing pad conductive element and a first plurality of dummy conductive elements electrically separated from each other and electrically separated from the first landing pad conductive element;

a polymer layer disposed over the interconnect structure;

a first plurality of metal pillars each disposed in an opening in the polymer layer, wherein the first plurality of metal pillars are electrically separated from each other and electrically separated from the first landing pad conductive element; and

a first bump electrically connected to the first landing pad conductive element, wherein the first plurality of metal pillars surrounds the first bump in a plan view.

19. The semiconductor device of claim 18, further comprising:

a second bump having a second plurality of metal pillars surrounding the second bump in the plan view.

20. The semiconductor device of claim 18, wherein the first plurality of metal pillars surrounding the first bump are each spaced a first distance from the first bump.