Protrusion bump pads for bond-on-trace processing

• US 10,522,495 B2
• Filed: 06/29/2018
• Issued: 12/31/2019
• Est. Priority Date: 01/06/2014
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Liang, Yu-Min, Wu, Jiun Yi
• Primary Examiner(s): Booth, Richard A
• Application Number:
  US16/023,292
• Publication Number:
  US 20180323163A1
• Time in Patent Office: 550 Days
• CPC Class Codes: H01L 21/4853 Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
• CPC Class Codes: H01L 21/4857 Multilayer substrates multilayer metallisation on monolayer substrate H01L21/4846
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/13082 Two-layer arrangements
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/16157 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16238 the bump connector connecting to a bonding area protruding from the surface of the item
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 23/49811 Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads H01L23/49827 takes precedence
• CPC Class Codes: H01L 23/49822 Multilayer substrates multilayer metallisation on monolayer substrate H01L23/498
• CPC Class Codes: H01L 23/49838 Geometry or layout
• CPC Class Codes: H01L 23/49866 characterised by the materials materials of the substrates H01L23/14, of the lead-frames H01L23/49579
• CPC Class Codes: H01L 24/16 of an individual bump connector
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/014 Solder alloys
• CPC Class Codes: H01L 2924/12042 LASER
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/381 : Pitch distance
• CPC Class Codes: H01L 2924/3841 : Solder bridging
• CPC Class Codes: H05K 1/111 : Pads for surface mounting, e.g. lay-out
• CPC Class Codes: H05K 2201/0367 : Metallic bump or raised conductor not used as solder bump solder materials or compositions and methods of application thereof H05K3/3457
• CPC Class Codes: H05K 2201/10674 : Flip chip
• CPC Class Codes: H05K 3/4007 : Surface contacts, e.g. bumps H05K3/4092 takes precedence; deposition of finish layers on pads H05K3/24; forming solder bumps H05K3/3457
• CPC Class Codes: H05K 3/4682 : Manufacture of core-less build-up multilayer circuits on a temporary carrier or on a metal foil

Abstract

An embodiment apparatus includes a dielectric layer, a conductive trace in the dielectric layer, and a bump pad. The conductive trace includes a first portion having an exposed top surface, wherein the exposed top surface is recessed from a top surface of the dielectric layer. Furthermore, the bump pad is disposed over and is electrically connected to a second portion of the conductive trace.

Claims

1. A method comprising:

forming a first conductive pad over a substrate;

forming a conductive trace over the substrate, a first region of the conductive trace contacting the first conductive pad, the conductive trace and the first conductive pad having different material compositions;

depositing a dielectric layer around the first conductive pad and the conductive trace; and

recessing a second region of the conductive trace below a top surface of the dielectric layer using an etch process which etches the conductive trace at a faster rate than the first conductive pad.

2. The method of claim 1, wherein the substrate comprises a seed layer on a substrate core, wherein forming the first conductive pad comprises plating the first conductive pad directly on the seed layer, and wherein forming the conductive trace comprises:

plating the first region of the conductive trace directly on the first conductive pad; and

plating the second region of the conductive trace directly on the seed layer.

3. The method of claim 2 further comprising while forming the conductive trace, plating a second conductive pad directly on the seed layer, wherein the conductive trace electrically connects the first conductive pad to the second conductive pad.

4. The method of claim 3, wherein the second conductive pad is connected to a conductive via providing electrical connection through the dielectric layer.

5. The method of claim 1 further comprising prior to recessing the second region of the conductive trace below a lot surface of the dielectric layer, separating at least a portion of the substrate from the dielectric layer.

6. The method of claim 5, wherein separating at least the portion of the substrate from the dielectric layer comprises using a mechanical wedge placed between a seed layer of the substrate and the dielectric layer.

7. The method of claim 6, wherein the etching process removes the seed layer.

8. The method of claim 1, wherein the first conductive pad comprises nickel or tin, and wherein the conductive trace comprises copper.

9. A method comprising:

plating a conductive pad over a substrate;

plating a conductive line over the substrate, wherein the conductive pad contacts a first portion of the conductive line, and wherein the conductive line and the conductive pad have different material compositions;

depositing an insulating layer around the conductive pad and the conductive line;

removing the substrate; and

after removing the substrate, etching a second portion of the conductive line.

10. The method of claim 9, wherein the conductive pad comprises nickel or tin, and wherein the conductive line comprises copper.

11. The method of claim 9 further comprising plating a contact pad electrically connected to the conductive pad through the conductive line, wherein the contact pad is disposed in the insulating layer, and wherein the method further comprises forming a conductive pillar extending from the contact pad through the insulating layer.

12. The method of claim 11, wherein the contact pad and the conductive line are plated simultaneously.

13. The method of claim 11 further comprising after removing the substrate, etching the contact pad.

14. The method of claim 13, wherein etching the contact pad is simultaneous with etching the conductive line.

15. The method of claim 9 further comprising bonding an integrated circuit chip to the conductive pad with a solder region physically coupling the integrated circuit chip to the conductive pad.

16. The method of claim 9, wherein etching the second portion of the conductive line recesses a surface of the conductive line away from a nearest surface of the insulating layer.

17. A method comprising:

plating a conductive pad over a substrate;

plating a conductive line over the substrate, wherein the conductive pad contacts a first portion of the conductive line, and wherein the conductive line and the conductive pad have different material compositions;

depositing an insulating layer around the conductive pad and the conductive line;

removing the substrate; and

after removing the substrate, etching a second portion of the conductive line to recess a top surface of the second portion of the conductive line below a top surface of the insulating layer.

18. The method of claim 17, wherein etching the second portion of the conductive line comprises using an etchant that etches the conductive line at a faster rate than the conductive pad.

19. The method of claim 17 comprising bonding an integrated circuit chip to the conductive pad with a solder region physically coupling the integrated circuit chip to the conductive pad.

20. The method of claim 17, wherein the conductive pad comprises nickel or tin, and wherein the conductive line comprises copper.