Double rule integrated circuit layouts for a dual transmission gate

• US 10,522,542 B1
• Filed: 06/28/2018
• Issued: 12/31/2019
• Est. Priority Date: 06/28/2018
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Peng, Shih-Wei, Zhuang, Hui-Zhong, Tzeng, Jiann-Tyng, Tien, Li-Chun, Sue, Pin-Dai, Lin, Wei-Cheng
• Primary Examiner(s): Dang, Phuc T
• Application Number:
  US16/021,847
• Publication Number:
  US 20200006338A1
• Time in Patent Office: 551 Days
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H03K 17/102 in field-effect transistor switches
• CPC Class Codes: H03K 17/122 in field-effect transistor switches
• CPC Class Codes: H03K 17/6872 using complementary field-effect transistors
• CPC Class Codes: H03K 2217/0054 Gating switches, e.g. pass gates

Abstract

Exemplary embodiments of an exemplary dual transmission gate and various exemplary integrated circuit layouts for the exemplary dual transmission gate are disclosed. These exemplary integrated circuit layouts represent double-height, also referred to as double rule, integrated circuit layouts. These double rule integrated circuit layouts include a first group of rows from among multiple rows of an electronic device design real estate and a second group of rows from among the multiple rows of the electronic device design real estate to accommodate a first metal layer of a semiconductor stack. The first group of rows can include a first pair of complementary metal-oxide-semiconductor field-effect (CMOS) transistors, such as a first p-type metal-oxide-semiconductor field-effect (PMOS) transistor and a first n-type metal-oxide-semiconductor field-effect (NMOS) transistor, and the second group of rows can include a second pair of CMOS transistors, such as a second PMOS transistor and a second NMOS transistor. These exemplary integrated circuit layouts disclose various configurations and arrangements of various geometric shapes that are situated within an oxide diffusion (OD) layer, a polysilicon layer, a metal diffusion (MD) layer, the first metal layer, and/or a second metal layer of a semiconductor stack. In the exemplary embodiments to follow, the various geometric shapes within the first metal layer are situated within the multiple rows of the electronic device design real estate and the various geometric shapes within the OD layer, the polysilicon layer, the MD layer, and/or the second metal layer are situated within multiple columns of the electronic device design real estate.

Claims

1. A dual transmission gate, comprising:

a first p-type metal-oxide-semiconductor field-effect (PMOS) transistor, situated within a first row from among a plurality of rows of an electronic device design real estate, configured to receive a first clocking signal;

a first n-type metal-oxide-semiconductor field-effect (NMOS) transistor situated within a second row from among the plurality of rows, configured to receive a second clocking signal;

a second PMOS transistor situated within a third row from among the plurality of rows, configured to receive the second clocking signal;

a second NMOS transistor situated within a fourth row from among the plurality of rows, configured to receive the first clocking signal;

a first region and a second region corresponding to the first clocking signal situated within a first interconnection layer of a semiconductor stack along the first row and the fourth row, respectively; and

a third region, situated within a second interconnection layer of the semiconductor stack along a first column from among a plurality of columns of the electronic device design real estate, configured to electrically connect the first region and the second region.

2. The dual transmission gate of claim 1, wherein the first region is configured to electrically connect to a first region of polysilicon material situated within a polysilicon layer of the semiconductor stack along a second column from among the plurality of columns, the first region of polysilicon material being configured to form a first gate region of the first PMOS transistor, and

wherein the second region is configured to electrically connect to a second region of polysilicon material situated within the polysilicon layer of the semiconductor stack along the second column, the second region of polysilicon material being configured to form a second gate region of the second NMOS transistor.

3. The dual transmission gate of claim 1, wherein the first interconnection layer comprises:

a first metal layer of the semiconductor stack, and

wherein the second interconnection layer comprises;

a polysilicon layer of the semiconductor stack;

an oxide diffusion (OD) layer of the semiconductor stack;

or

a second metal layer of the semiconductor stack.

4. The dual transmission gate of claim 1, further comprising:

a fourth region corresponding to the second clocking signal situated within the first interconnection layer along the third row,

wherein the fourth region is configured to electrically connect to a first region of polysilicon material situated within a polysilicon layer of the semiconductor stack along a second column from among the plurality of columns, the first region of polysilicon material being configured to form a first gate region of the first NMOS transistor and a first gate region of the second PMOS transistor.

5. The dual transmission gate of claim 1, further comprising:

a fourth region corresponding to a first input terminal of the dual transmission gate situated along a second column from among the plurality of columns, the fourth region being configured to form a first source/drain region of the first PMOS transistor and a first source/drain region of the first NMOS transistor; and

a fifth region corresponding to a second input terminal of the dual transmission gate situated along the second column, the fifth region being configured to form a first source/drain region of the second PMOS transistor and a first source/drain region of the second NMOS transistor.

6. The dual transmission gate of claim 5, further comprising:

a sixth region of conductive material corresponding to an output terminal of the dual transmission gate situated along a third column from among the plurality of columns, the sixth region being configured to form a second source/drain region of the first PMOS transistor, a second source/drain region of the first NMOS transistor, a second source/drain region of the second PMOS transistor, and a second source/drain region of the second NMOS transistor.

7. The dual transmission gate of claim 1, wherein at least two of the first PMOS transistor, the first NMOS transistor, the second PMOS transistor, and the second NMOS transistor are situated along a second column from among the plurality of columns.

8. The dual transmission gate of claim 7, wherein the second PMOS transistor and the second NMOS transistor are situated along a third column from among the plurality of columns.

9. The dual transmission gate of claim 1, further comprising:

a fourth region and a fifth region corresponding to the second clocking signal situated within the first interconnection layer of the semiconductor stack,

wherein the fourth region is configured to electrically connect to a first region of polysilicon material situated within a polysilicon layer of the semiconductor stack along a second column from among the plurality of columns, the first region of polysilicon material being configured to form a first gate region of the first NMOS transistor, and

wherein the fifth region is configured to electrically connect to a second region of polysilicon material situated within the polysilicon layer along the second column, the fifth region of polysilicon material being configured to form a second gate region of the second PMOS transistor; and

a sixth region, situated within the second interconnection layer of the semiconductor stack along a third column from among the plurality of columns, configured to electrically connect the fourth region and the fifth region.