FinFET devices with dummy fins having multiple dielectric layers

• US 10,522,546 B2
• Filed: 04/20/2018
• Issued: 12/31/2019
• Est. Priority Date: 04/20/2018
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Liaw, Jhon Jhy
• Primary Examiner(s): Turner, Brian
• Application Number:
  US15/958,542
• Publication Number:
  US 20190326287A1
• Time in Patent Office: 620 Days
• CPC Class Codes: H01L 21/0274 Photolithographic processes
• CPC Class Codes: H01L 21/823814 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/823821 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823878 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 27/0924 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/6681 using dummy structures having essentially the same shape as the semiconductor body, e.g. to provide stability

Abstract

A semiconductor device includes a substrate; semiconductor fins over the substrate and oriented lengthwise along a first direction; first multi-dielectric-layer (MDL) fins and second MDL fins over the substrate and oriented lengthwise along the first direction, wherein the first and the second MDL fins are intermixed with the semiconductor fins, wherein each of the first MDL fins and the second MDL fins includes an outer dielectric layer and an inner dielectric layer, wherein the outer dielectric layer and the inner dielectric layer have different dielectric materials; and gate structures oriented lengthwise along a second direction generally perpendicular to the first direction, wherein the gate structures are spaced from each other along the first direction, and are separated by the first MDL fins along the second direction, wherein the gate structures engage the semiconductor fins and the second MDL fins.

Claims

1. A semiconductor device, comprising:

a substrate;

semiconductor fins over the substrate and oriented lengthwise along a first direction;

first multi-dielectric-layer (MDL) fins and second MDL fins over the substrate and oriented lengthwise along the first direction, wherein the first and the second MDL fins are intermixed with the semiconductor fins, wherein each of the first MDL fins and the second MDL fins includes an outer dielectric layer and an inner dielectric layer, wherein the outer dielectric layer and the inner dielectric layer have different dielectric materials; and

gate structures oriented lengthwise along a second direction generally perpendicular to the first direction, wherein the gate structures are spaced from each other along the first direction, and are separated by the first MDL fins along the second direction, wherein the gate structures engage sidewalls and a top surface of each of the semiconductor fins and sidewalls and a top surface of each of the second MDL fins, wherein the top surface of each of the second MDL faces away from the substrate.

2. The semiconductor device of claim 1, wherein the outer dielectric layer of the second MDL fins is taller than the outer dielectric layer of the first MDL fins.

3. The semiconductor device of claim 1, wherein the inner dielectric layer of the second MDL fins is taller than the inner dielectric layer of the first MDL fins.

4. The semiconductor device of claim 1, wherein a dielectric material of the outer dielectric layer of the first and the second MDL fins has a lower dielectric constant than a dielectric material of the inner dielectric layer of the first and the second MDL fins.

5. The semiconductor device of claim 4, wherein the dielectric material of the outer dielectric layer of the first and the second MDL fins has a dielectric constant equal to or less than 5, and the dielectric material of the inner dielectric layer of the first and the second MDL fins has a dielectric constant equal to or greater than 7.

6. The semiconductor device of claim 4, wherein a top surface of the inner dielectric layer of the first MDL fins is higher than a top surface of the outer dielectric layer of the first MDL fins, and a top surface of the inner dielectric layer of the second MDL fins is higher than a top surface of the outer dielectric layer of the second MDL fins.

7. The semiconductor device of claim 1, wherein a dielectric material of the outer dielectric layer of the first and the second MDL fins has a higher dielectric constant than a dielectric material of the inner dielectric layer of the first and the second MDL fins.

8. The semiconductor device of claim 7, wherein the dielectric material of the inner dielectric layer of the first and the second MDL fins has a dielectric constant equal to or less than 5, and the dielectric material of the outer dielectric layer of the first and the second MDL fins has a dielectric constant equal to or greater than 7.

9. The semiconductor device of claim 7, wherein a top surface of the inner dielectric layer of the first MDL fins is lower than a top surface of the outer dielectric layer of the first MDL fins, and a top surface of the inner dielectric layer of the second MDL fins is lower than a top surface of the outer dielectric layer of the second MDL fins.

10. The semiconductor device of claim 1, wherein the first MDL fins are wider than the second MDL fins along the second direction.

11. The semiconductor device of claim 1, wherein the first MDL fins include one more dielectric layer than the second MDL fins.

12. The semiconductor device of claim 1, further comprising a third MDL fin over the substrate and oriented lengthwise along the first direction, wherein the third MDL fin includes one more dielectric layer than the first and the second MDL fins.

13. The semiconductor device of claim 1, further comprising epitaxial S/D features having their widths confined by the adjacent first and second MDL fins along the second direction.

14. A semiconductor device, comprising:

a substrate;

semiconductor fins over the substrate and oriented lengthwise along a first direction, wherein some of the semiconductor fins are of N-conductivity type, and some of the semiconductor fins are of P-conductivity type;

first multi-dielectric-layer (MDL) fins and second MDL fins over the substrate and oriented lengthwise along the first direction, wherein each of the first MDL fins is positioned between two of the semiconductor fins that are of a same conductivity type, and each of the second MDL fins is positioned between two of the semiconductor fins that are of opposite conductivity types, wherein each of the first MDL fins and the second MDL fins includes an outer dielectric layer and an inner dielectric layer, wherein the outer dielectric layer includes a first dielectric material, and the inner dielectric layer includes a second dielectric material that has a different dielectric constant than the first dielectric material; and

gate structures oriented lengthwise along a second direction generally perpendicular to the first direction, wherein the gate structures are spaced from each other along the first direction, and are separated by the first MDL fins along the second direction, wherein the gate structures engage the semiconductor fins and the second MDL fins.

15. The semiconductor device of claim 14, wherein the first dielectric material has a dielectric constant equal to or less than 5, and the second dielectric material has a dielectric constant equal to or greater than 7.

16. The semiconductor device of claim 14, wherein the second dielectric material has a dielectric constant equal to or less than 5, and the first dielectric material has a dielectric constant equal to or greater than 7.

17. The semiconductor device of claim 14, wherein the first MDL fins and the second MDL fins are placed alternatingly along the second direction, and there is only one semiconductor fin between two adjacent first and second MDL fins.

18. The semiconductor device of claim 14, wherein the first MDL fins and the second MDL fins are placed alternatingly along the second direction, wherein two or more semiconductor fins of a same conductivity type are positioned between two adjacent first and second MDL fins.

19. A semiconductor device, comprising:

a substrate;

CMOS cells formed over the substrate, wherein each CMOS cell includes an N-conductivity type semiconductor fin and a P-conductivity type semiconductor fin oriented lengthwise along a first direction and further includes a first multi-dielectric-layer (MDL) fin oriented lengthwise along the first direction and positioned between the N-conductivity type and the P-conductivity type semiconductor fins, wherein each CMOS cell further includes a gate structure engaging the N-conductivity type and the P-conductivity type semiconductor fins and the first MDL fin; and

second MDL fins over the substrate, oriented lengthwise along the first direction, and positioned between the CMOS cells, wherein each of the first MDL fins and the second MDL fins includes an outer dielectric layer and an inner dielectric layer, wherein the outer dielectric layer includes a first dielectric material, and the inner dielectric layer includes a second dielectric material that has a different dielectric constant than the first dielectric material.

20. The semiconductor device of claim 19, wherein the first dielectric material has a dielectric constant equal to or less than 5, and the second dielectric material has a dielectric constant equal to or greater than 7.