SRAM cell with balanced write port

• US 10,522,553 B2
• Filed: 07/27/2018
• Issued: 12/31/2019
• Est. Priority Date: 06/16/2017
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Hsu, Kuo-Hsiu, Lin, Yu-Kuan, Chang, Feng-Ming, Hung, Lien Jung, Wang, Ping-Wei
• Primary Examiner(s): Junge, Bryan R
• Application Number:
  US16/047,586
• Publication Number:
  US 20180366469A1
• Time in Patent Office: 522 Days
• CPC Class Codes: G11C 11/412 using field-effect transistors only
• CPC Class Codes: G11C 11/413 Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
• CPC Class Codes: G11C 11/419 Read-write [R-W] circuits
• CPC Class Codes: H01L 27/0924 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H10B 10/12 comprising a MOSFET load element

Abstract

A semiconductor device includes first, second, third, and fourth active regions arranged along a first direction. The first, second, third, and fourth active regions includes channel regions and source/drain (S/D) regions of first, second, third, and fourth transistors respectively, the first and fourth transistors are of a first conductivity type, and the second and third transistors are of a second conductivity type opposite the first conductivity type. The semiconductor device further includes a fifth active region between the second and third active regions. The fifth active region includes channel regions and S/D regions of fifth and sixth transistors that are of same conductivity type. The semiconductor device further includes first, second, third, fourth, fifth, and sixth gates. The first through sixth gates are disposed over the channel regions of the first through sixth transistors respectively. The first, second, and fifth gates are electrically connected.

Claims

1. A semiconductor device, comprising:

first, second, third, and fourth active regions arranged in order from first to fourth along a first direction, wherein the first, second, third, and fourth active regions comprise channel regions and source/drain (S/D) regions of first, second, third, and fourth transistors respectively, the first and fourth transistors are of a first conductivity type, and the second and third transistors are of a second conductivity type opposite the first conductivity type;

a fifth active region between the second and third active regions, wherein the fifth active region comprises channel regions and S/D regions of fifth and sixth transistors that are of same conductivity type;

first, second, third, fourth, fifth, and sixth gates, wherein the first through sixth gates are disposed over the channel regions of the first through sixth transistors respectively, wherein the first, second, and fifth gates are electrically connected, and the third and fourth gates are electrically connected;

one or more first conductive features that electrically connect one of the S/D regions of the first transistor, one of the S/D regions of the second transistor, and the third gate; and

one or more second conductive features that electrically connect the fifth gate, one of the S/D regions of the third transistor, and one of the S/D regions of the fourth transistor.

2. The semiconductor device of claim 1, wherein the one or more first conductive features include:

a contact feature disposed over the one of the S/D regions of the second transistor; and

a local interconnect disposed directly over the contact feature and the fifth gate.

3. The semiconductor device of claim 1, wherein the one or more first conductive features include a conductive feature that is disposed over and insulated from one of the S/D regions of the fifth and sixth transistors.

4. The semiconductor device of claim 1, wherein the first, second, and fifth gate share a common metal layer.

5. The semiconductor device of claim 1, wherein the first active region further comprises a channel region and S/D regions of a seventh transistor, and the fourth active region further comprises a channel region and S/D regions of an eighth transistor.

6. The semiconductor device of claim 5, further comprising seventh and eighth gates, wherein the seventh and eighth gates are disposed over the channel regions of the seventh and eighth transistors respectively.

7. The semiconductor device of claim 1, wherein each of the first through sixth transistors are FinFETs.

8. The semiconductor device of claim 1, wherein the fifth and sixth transistors share a common S/D region.

9. The semiconductor device of claim 1, wherein the fifth and sixth transistors are of the first conductivity type.

10. The semiconductor device of claim 1, wherein the fifth and sixth transistors are of the second conductivity type.

11. A semiconductor device, comprising:

first, second, third, and fourth transistors arranged in order from first to fourth along a first direction, wherein the first and fourth transistors are NMOS FET, the second and third transistors are PMOS FET, and each of the first through fourth transistors comprises a channel region, two source/drain (S/D) regions, and a gate stack over the respective channel region; and

fifth and sixth transistors between the second and third transistors, wherein the fifth and sixth transistors are of a same conductivity type, and each of the fifth and sixth transistors comprises a channel region, two source/drain (S/D) regions, and a gate stack over the respective channel region,

wherein the gate stacks of the first, second, and fifth transistors, one of the S/D regions of the third transistor, and one of the S/D regions of the fourth transistor are electrically connected, and

wherein the gate stacks of the third and fourth transistors, one of the S/D regions of the first transistor, and one of the S/D regions of the second transistor are electrically connected.

12. The semiconductor device of claim 11, wherein the fifth and sixth transistors are PMOS FETs.

13. The semiconductor device of claim 11, wherein the fifth and sixth transistors are NMOS FETs.

14. The semiconductor device of claim 11, wherein the first through sixth transistors are FinFETs.

15. A semiconductor device, comprising:

first, second, third, and fourth FinFETs arranged in order from first to fourth along a first direction, wherein the first and fourth transistors are of a first conductivity type, the second and third transistors are of a second conductivity type opposite the first conductivity type, and each of the first through fourth transistors comprises a channel region, two source/drain (S/D) regions, and a gate stack over the respective channel region; and

fifth and sixth FinFETs between the second and third FinFETs, wherein the fifth and sixth FinFETs are of a same conductivity type, and each of the fifth and sixth transistors comprises a channel region, two source/drain (S/D) regions, and a gate stack over the respective channel region,

wherein the gate stacks of the first, second, and fifth FinFETs, one of the S/D regions of the third FinFET, and one of the S/D regions of the fourth FinFET are electrically connected,

wherein the gate stacks of the third and fourth FinFETs, one of the S/D regions of the first FinFET, and one of the S/D regions of the second FinFET are electrically connected, and

wherein the fifth and sixth FinFETs share a common S/D region.

16. The semiconductor device of claim 15, wherein the first conductivity type is n-type and the second conductivity type is p-type.

17. The semiconductor device of claim 15, wherein the fifth and sixth FinFETs are of the first conductivity type.

18. The semiconductor device of claim 15, wherein the fifth and sixth FinFETs are of the second conductivity type.

19. The semiconductor device of claim 15, wherein the channel regions of the fifth and sixth FinFETs are in a same fin.

20. The semiconductor device of claim 15, wherein the gate stacks of the first, second, and fifth FinFETs share a common metal layer.