Germanium nitride layers on semiconductor structures, and methods for forming the same

• US 10,522,623 B1
• Filed: 08/15/2018
• Issued: 12/31/2019
• Est. Priority Date: 08/15/2018
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Holland, Martin Christopher, Vellianitis, Georgios
• Primary Examiner(s): Shook, Daniel P
• Application Number:
  US15/998,683
• Time in Patent Office: 503 Days
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: H01L 21/02112 characterised by the material of the layer
• CPC Class Codes: H01L 21/02271 deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition H01L21/02266 takes precedence
• CPC Class Codes: H01L 21/0228 deposition by cyclic CVD, e.g. ALD, ALE, pulsed CVD
• CPC Class Codes: H01L 21/02381 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02532 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02603 Nanowires
• CPC Class Codes: H01L 29/0673 oriented parallel to a substrate
• CPC Class Codes: H01L 29/1033 with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with channel and gate aligned in the lengthwise direction H01L29/42376; with buried channel H01L29/7838
• CPC Class Codes: H01L 29/16 including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
• CPC Class Codes: H01L 29/42364 characterised by the insulating layer, e.g. thickness or uniformity H01L29/42324 and H01L29/4234 take precedence
• CPC Class Codes: H01L 29/42392 fully surrounding the channel, e.g. gate-all-around
• CPC Class Codes: H01L 29/518 the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
• CPC Class Codes: H01L 29/66439 with a one- or zero-dimensional channel, e.g. quantum wire FET, in-plane gate transistor [IPG], single electron transistor [SET], striped channel transistor, Coulomb blockade transistor with an active layer made of a group 13/15 material H01L29/66469
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/775 with one dimensional charge carrier gas channel, e.g. quantum wire FET
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

Provided herein are semiconductor structures that include germanium and have a germanium nitride layer on the surface, as well as methods of forming the same. The described structures include nanowires and fins. Methods of the disclosure include metal-organic chemical vapor deposition with a germanium precursor. The described methods also include using a N₂H₄ vapor.

Claims

1. A method, comprising:

forming a semiconductor structure on a substrate, the semiconductor structure comprising germanium;

forming a channel region in the semiconductor structure;

forming a germanium nitride layer on the channel region, the germanium nitride layer having a thickness that is more than a monolayer;

forming a first dielectric layer over the germanium nitride layer; and

forming a gate electrode over the first dielectric layer.

2. The method of claim 1, wherein the forming the germanium nitride layer comprises metal-organic chemical vapor deposition (MOCVD).

3. The method of claim 2, wherein the MOCVD comprises exposing the semiconductor structure to a vapor comprising Ge₂H₆.

4. The method of claim 3, wherein the vapor further comprises N₂H₄.

5. The method of claim 4, wherein the vapor is anhydrous.

6. The method of claim 5, wherein the semiconductor structure, during the forming the germanium nitride layer, is at a temperature of no more than about 500°

C.

7. The method of claim 5, wherein the semiconductor structure is exposed to the vapor at a pressure of no more than about 100 Torr.

8. The method of claim 1, wherein the semiconductor structure is a nanowire.

9. A method, comprising:

forming a first nanowire on a substrate, the first nanowire comprising a germanium-containing material;

forming a first germanium nitride layer over the first nanowire, the first germanium nitride layer extending completely around a perimeter of the first nanowire in a cross-section perpendicular to a longitudinal axis of the first nanowire;

forming a first dielectric layer over the first germanium nitride layer; and

forming a gate electrode over the first dielectric layer.

10. The method of claim 9, wherein the first dielectric layer completely covers the first germanium nitride layer.

11. The method of claim 9 further comprising:

forming a second nanowire above the first nanowire;

forming a second germanium nitride layer over the second nanowire, the second germanium nitride layer extending completely around a perimeter of the second nanowire in a cross-section perpendicular to a longitudinal axis of the second nanowire, the second germanium nitride layer being discontinuous from the first germanium nitride layer; and

forming a second dielectric layer over the second germanium nitride layer;

wherein the gate electrode extends over the second dielectric layer.

12. The method of claim 11, wherein the gate electrode extends between the first nanowire and the second nanowire.

13. The method of claim 11, wherein the first dielectric layer is separated from the second dielectric layer.

14. The method of claim 9, wherein an interface trap density (D_IT) of an interface between the first nanowire and the first germanium nitride layer is less than about 5×

10¹¹ eV<sup>−

1</sup> cm<sup>−

2</sup>.

15. The method of claim 9, wherein the first germanium nitride layer is free of oxygen.

16. The method of claim 9, wherein a carbon concentration of the first germanium nitride layer is no more than about 5×

10¹⁶ atoms/cm<sup>−

3</sup>.

17. A method, comprising:

forming a first nanowire and a second nanowire on a substrate, the first nanowire and the second nanowire comprising a germanium-containing material;

forming a source region and a drain region, the first nanowire and the second nanowire being interposed between the source region and the drain region;

exposing the first nanowire and the second nanowire to a nitrogen-containing vapor to form a first germanium nitride layer over the first nanowire and a second germanium nitride layer over the second nanowire, the first germanium nitride layer being separated from the second germanium nitride layer;

forming a first dielectric layer over the first germanium nitride layer and a second dielectric layer over the second germanium nitride layer; and

forming a gate electrode over the first dielectric layer and the second dielectric layer.

18. The method of claim 17, wherein the nitrogen-containing vapor is free of carbon.

19. The method of claim 18, wherein the nitrogen-containing vapor comprises N₂H₄.

20. The method of claim 19, wherein N₂H₄ is anhydrous.