Multi-gate device and method of fabrication thereof
First Claim
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1. A method of forming a semiconductor device, the method comprising:
- providing a fin extending from a substrate, the fin having a source/drain region and a channel region, wherein the fin includes a first layer disposed over the substrate, a second layer disposed over the first layer, and a third layer disposed over the second layer;
removing at least a portion of the second layer from the channel region to form a gap between the first and third layers;
forming a first material in the channel region to form a first interfacial layer portion at least partially wrapping around the first layer and a second interfacial layer portion at least partially wrapping around the third layer;
depositing a second material in the channel region to form a high-k dielectric layer at least partially wrapping around the first interfacial layer portion and the second interfacial layer portion; and
forming a metal layer along opposing sidewalls of the high-k dielectric layer the channel region.
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Abstract
A semiconductor device includes a fin extending from a substrate. The fin has a source/drain region and a channel region. The channel region includes a first semiconductor layer and a second semiconductor layer disposed over the first semiconductor layer and vertically separated from the first semiconductor layer by a spacing area. A high-k dielectric layer at least partially wraps around the first semiconductor layer and the second semiconductor layer. A metal layer is formed along opposing sidewalls of the high-k dielectric layer. The metal layer includes a first material. The spacing area is free of the first material.
38 Citations
20 Claims
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1. A method of forming a semiconductor device, the method comprising:
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providing a fin extending from a substrate, the fin having a source/drain region and a channel region, wherein the fin includes a first layer disposed over the substrate, a second layer disposed over the first layer, and a third layer disposed over the second layer; removing at least a portion of the second layer from the channel region to form a gap between the first and third layers; forming a first material in the channel region to form a first interfacial layer portion at least partially wrapping around the first layer and a second interfacial layer portion at least partially wrapping around the third layer; depositing a second material in the channel region to form a high-k dielectric layer at least partially wrapping around the first interfacial layer portion and the second interfacial layer portion; and forming a metal layer along opposing sidewalls of the high-k dielectric layer the channel region. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A method, comprising:
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forming a fin element including first, second, and third semiconductor layers; removing at least a portion of the second semiconductor layer from a channel region of the fin element to form a gap between the first and third semiconductor layers; forming an interposing feature in the channel region, wherein the interposing feature includes; a first interfacial layer portion at least partially wrapping around the first semiconductor layer; a second interfacial layer portion at least partially wrapping around the third semiconductor layer; a dielectric layer at least partially wrapping around the first interfacial layer portion and the second interfacial layer portion; and depositing a metal layer at least partially wrapping around the interposing feature; removing at least a portion of the second layer from the channel region to form a gap between the first and third layers; forming a first material in the channel region to form a first interfacial layer portion at least partially wrapping around the first layer and a second interfacial layer portion at least partially wrapping around the third layer; depositing a second material in the channel region to form a high-k dielectric layer at least partially wrapping around the first interfacial layer portion and the second interfacial layer portion; and forming a metal layer along opposing sidewalls of the high-k dielectric layer the channel region. - View Dependent Claims (9, 10, 11, 12, 13, 14)
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15. A method, comprising:
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providing a substrate including a fin element, the fin element including a bottom layer disposed over the substrate, a middle layer disposed over the bottom layer, and a top layer disposed over the middle layer; forming a dummy gate structure in a channel region of the fin element; forming a source/drain feature in a source/drain region of the fin element adjacent to the dummy gate structure; removing the dummy gate structure to form an opening in the channel region to expose the fin element in the channel region; removing at least a portion of the middle layer of the fin element exposed in the opening; forming an interposing feature in the channel region, wherein the forming the interposing feature includes; forming a first material in the channel region to form a first interfacial layer portion at least partially wrapping around the bottom layer and a second interfacial layer portion at least partially wrapping around the top layer; forming a metal layer along opposing sidewalls of the interposing feature in the channel region, wherein the metal layer includes a scavenging material; and causing a scavenging process to the first and second interfacial layer portions by performing an annealing process to the metal layer. - View Dependent Claims (16, 17, 18, 19, 20)
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Specification