Lattice-mismatched semiconductor structures with reduced dislocation defect densities and related methods for device fabrication

• US 10,522,629 B2
• Filed: 12/07/2017
• Issued: 12/31/2019
• Est. Priority Date: 05/17/2005
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Li, Jizhong, Lochtefeld, Anthony J.
• Primary Examiner(s): Slutsker, Julia
• Application Number:
  US15/835,162
• Publication Number:
  US 20180108741A1
• Time in Patent Office: 754 Days
• CPC Class Codes: H01L 21/02381 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02433 Crystal orientation
• CPC Class Codes: H01L 21/02521 Materials
• CPC Class Codes: H01L 21/02609 Crystal orientation
• CPC Class Codes: H01L 21/02639 Preparation of substrate for selective deposition
• CPC Class Codes: H01L 21/02647 Lateral overgrowth
• CPC Class Codes: H01L 21/7624 using semiconductor on insulator [SOI] technology H01L21/76297 takes precedence; manufacture of integrated circuits on insulating substrates H01L21/84; silicon on sapphire [SOS] technology H01L21/86
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/8252 the substrate being a semiconductor, using III-V technology H01L21/8258 takes precedence
• CPC Class Codes: H01L 21/8258 the substrate being a semiconductor, using a combination of technologies covered by H01L21/8206, H01L21/8213 , H01L21/822, H01L21/8252, H01L21/8254 or H01L21/8256
• CPC Class Codes: H01L 27/0605 integrated circuits made of compound material, e.g. AIIIBV
• CPC Class Codes: H01L 29/045 by their particular orientation of crystalline planes
• CPC Class Codes: H01L 29/1054 with a variation of the composition, e.g. channel with strained layer for increasing the mobility
• CPC Class Codes: H01L 29/205 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 31/036 characterised by their crystalline structure or particular orientation of the crystalline planes
• CPC Class Codes: H01L 31/0735 comprising only AIIIBV compound semiconductors, e.g. GaAs/AlGaAs or InP/GaInAs solar cells
• CPC Class Codes: H01L 33/0025 comprising only AIIIBV compounds
• CPC Class Codes: H01L 33/18 : within the light emitting region
• CPC Class Codes: H01S 5/22 : having a ridge or stripe structure
• CPC Class Codes: H01S 5/323 : in AIIIBV compounds, e.g. AlGaAs-laser, InP-based laser
• CPC Class Codes: Y02E 10/544 : Solar cells from Group III-V materials

Abstract

A method of forming a semiconductor structure includes forming an opening in a dielectric layer, forming a recess in an exposed part of a substrate, and forming a lattice-mismatched crystalline semiconductor material in the recess and opening.

Claims

1. A method of forming a semiconductor device comprising:

forming a dielectric material over a substrate comprising a first crystalline material;

patterning the dielectric material to expose a portion of the substrate;

forming a recess in the exposed portions of the substrate;

forming a second crystalline material protruding from the recess, wherein a first portion of the second crystalline material is disposed within the recess, wherein a second portion of the second crystalline material extends over a top surface of the dielectric material, wherein the second crystalline material is lattice mismatched to the first crystalline material;

forming a photonic device on the second portion of the second crystalline material;

removing the substrate to expose the first portion of the second crystalline material and the second portion of the second crystalline material; and

removing an end portion of the exposed first portion of the second crystalline material to form ridges comprising the remaining first portion of the second crystalline material, the ridges protruding from the second portion of the second crystalline material.

2. The method of claim 1, further comprising forming a third crystalline material within the recess prior to forming the second crystalline material, wherein the third crystalline material is lattice mismatched to the first crystalline material and the second crystalline material.

3. The method of claim 1 further comprising removing the dielectric material after removing the end portion of the exposed first portion of the second crystalline material.

4. The method of claim 1, wherein a spacing between adjacent ridges is less than or equal to a visible light wavelength.

5. The method of claim 1, wherein a width of one or more ridges is less than or equal to a visible light wavelength.

6. The method of claim 1, further comprising forming a metal contact on at least one ridge.

7. The method of claim 1, wherein removing an end portion of the exposed first portion of the second crystalline material comprises performing a chemical-mechanical polish (CMP).

8. The method of claim 1, wherein forming the photonic device comprises forming a light-emitting diode (LED).

9. The method of claim 1, wherein the exposed first portion of the second crystalline semiconductor material comprises a non-planar surface.

10. A method comprising:

forming a dielectric layer over a first surface of a semiconductor substrate, the thickness of the dielectric layer over the first surface being a first distance, the semiconductor substrate comprising a first semiconductor material;

forming a plurality of openings in the dielectric layer;

etching the first surface of the semiconductor substrate to form a plurality of grooves extending a second distance below the first surface of the semiconductor substrate;

depositing a second semiconductor material in the grooves, the second semiconductor material extending above the first surface of the semiconductor substrate, the second semiconductor material different from the first semiconductor material;

forming a photonic semiconductor structure on the second semiconductor material;

etching the semiconductor substrate to expose the second semiconductor material;

removing a first portion of the second semiconductor material, the first portion of the semiconductor material extending between the first distance and a sum of the first distance and the second distance into the exposed second semiconductor material, a remaining second portion of the second semiconductor material forming a plurality of raised features.

11. The method of claim 10, further comprising etching the dielectric layer after etching the semiconductor substrate.

12. The method of claim 10, wherein the plurality of raised features comprises a two-dimensional array of raised features.

13. The method of claim 10, wherein forming the photonic semiconductor structure comprises depositing a third semiconductor material on the second semiconductor material, the third semiconductor material different from the second semiconductor material.

14. The method of claim 10, further comprising forming a metal layer on the photonic semiconductor structure.

15. The method of claim 10, wherein the plurality of grooves comprise (111) surfaces of the first semiconductor material.

16. The method of claim 10, further comprising forming an etch-stop on the second semiconductor material.

17. A method comprising:

forming a crystalline semiconductor substrate comprising a plurality of ridges protruding a first height from a first surface, wherein a width of each ridge is less than or equal to a visible light wavelength and wherein a spacing between adjacent ridges is less than or equal to a visible light wavelength;

recessing the plurality of ridges, wherein after the recessing, the plurality of ridges protrude a second height from the first surface that is less than the first height; and

after recessing the plurality of ridges, forming a photonic structure on a second surface of the crystalline semiconductor substrate.

18. The method of claim 17, further comprising forming a metal contact on the plurality of ridges.

19. The method of claim 18, wherein the metal contact conforms to at least one ridge of the plurality of ridges.

20. The method of claim 17, further comprising forming a metal layer on a surface of the photonic structure that is opposite the crystalline semiconductor substrate.