Gate spacer structure of FinFET device

• US 10,522,653 B2
• Filed: 05/22/2019
• Issued: 12/31/2019
• Est. Priority Date: 04/28/2017
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Li, Chung-Ting, Wu, Bi-Fen, Lu, Jen-Hsiang, Chang, Chih-Hao
• Primary Examiner(s): Malsawma, Lex H
• Application Number:
  US16/419,292
• Publication Number:
  US 20190273150A1
• Time in Patent Office: 223 Days
• Field of Search: None
• CPC Class Codes: H01L 21/2815 part or whole of the electrode is a sidewall spacer or made by a similar technique, e.g. transformation under mask, plating
• CPC Class Codes: H01L 21/823418 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/823431 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823437 with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 21/823468 with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
• CPC Class Codes: H01L 21/823481 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 27/0886 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/41791 for transistors with a horizontal current flow in a vertical sidewall, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/6653 using the removal of at least part of spacer, e.g. disposable spacer
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/6681 using dummy structures having essentially the same shape as the semiconductor body, e.g. to provide stability
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

A method includes forming a fin extending above an isolation region. A sacrificial gate stack having a first sidewall and a second sidewall opposite the first sidewall is formed over the fin. A first spacer is formed on the first sidewall of the sacrificial gate stack. A second spacer is formed on the second sidewall of the sacrificial gate stack. A patterned mask having an opening therein is formed over the sacrificial gate stack, the first spacer and the second spacer. The patterned mask extends along a top surface and a sidewall of the first spacer. The second spacer is exposed through the opening in the patterned mask. The fin is patterned using the patterned mask, the sacrificial gate stack, the first spacer and the second spacer as a combined mask to form a recess in the fin. A source/drain region is epitaxially grown in the recess.

Claims

1. A device comprising:

a gate stack on sidewalls and over a top surface of a semiconductor fin, the gate stack having a first sidewall and a second sidewall opposite to the second sidewall;

a first spacer structure along the first sidewall of the gate stack, the first spacer structure comprising;

a first spacer, a first portion of the first spacer extending along the first sidewall of the gate stack, a second portion of the first spacer extending laterally away from the first sidewall of the gate stack and over the top surface of the semiconductor fin; and

a second spacer over the first spacer, the second spacer partially covering a top surface of the second portion of the first spacer; and

a second spacer structure along the second sidewall of the gate stack, the second spacer structure comprising;

a third spacer, a first portion of the third spacer extending along the second sidewall of the gate stack, a second portion of the third spacer extending laterally away from the second sidewall of the gate stack and over the top surface of the semiconductor fin; and

a fourth spacer over the third spacer, the fourth spacer fully covering a top surface of the second portion of the third spacer.

2. The device of claim 1, further comprising a first epitaxial region extending into the semiconductor fin adjacent the first spacer structure, wherein the first epitaxial region has a first volume.

3. The device of claim 2, further comprising a second epitaxial region extending into the semiconductor fin adjacent the second spacer structure, wherein the second epitaxial region has a second volume less than the first volume.

4. The device of claim 1, wherein the first spacer and the second spacer comprise different materials.

5. The device of claim 1, wherein the third spacer and the fourth spacer comprise different materials.

6. The device of claim 1, wherein the first spacer and the third spacer comprise a same material.

7. The device of claim 1, wherein the second spacer and the fourth spacer comprise a same material.

8. A device comprising:

a gate stack on sidewalls and over a top surface of a semiconductor fin, the gate stack having a first sidewall and a second sidewall opposite to the second sidewall;

a first spacer structure on the first sidewall of the gate stack, the first spacer structure comprising;

a first spacer on the first sidewall of the gate stack; and

a second spacer adjacent the first spacer, the first spacer being interposed between the second spacer and the first sidewall of the gate stack, a first portion of the first spacer extending laterally away from the first sidewall of the gate stack and beyond a sidewall of the second spacer, the sidewall of the second spacer facing away from the gate stack; and

a second spacer structure on the second sidewall of the gate stack, the second spacer structure comprising;

a third spacer on the second sidewall of the gate stack; and

a fourth spacer adjacent the third spacer, the third spacer being interposed between the fourth spacer and the second sidewall of the gate stack, a first portion of the third spacer extending laterally away from the second sidewall of the gate stack to a sidewall of the fourth spacer, the sidewall of the fourth spacer facing away from the gate stack.

9. The device of claim 8, further comprising a first epitaxial region extending into the semiconductor fin adjacent the first spacer structure, wherein the first epitaxial region has a first width.

10. The device of claim 9, further comprising a second epitaxial region extending into the semiconductor fin adjacent the second spacer structure, wherein the second epitaxial region has a second width less than the first width.

11. The device of claim 10, wherein the first epitaxial region is laterally spaced apart from the first sidewall of the gate stack by a first distance, and wherein the second epitaxial region is laterally spaced apart from the second sidewall of the gate stack by a second distance less than the first distance.

12. The device of claim 8, wherein a sidewall of the second spacer and a top surface of the first spacer form an angle between about 90 degrees and about 120 degrees.

13. The device of claim 8, wherein a topmost surface of the first spacer is level with a topmost surface of the second spacer.

14. The device of claim 8, wherein a width of the first portion of the first spacer is greater than a width of the first portion of the third spacer.

15. A device comprising:

a fin over a substrate;

a gate stack along sidewalls and over a top surface of a channel region of the fin, the gate stack having a first sidewall and a second sidewall opposite to the second sidewall;

a first gate spacer structure along the first sidewall of the gate stack, the first gate spacer structure comprising a first gate spacer, a first portion of the first gate spacer extending along the first sidewall of the gate stack, a second portion of the first gate spacer extending laterally away from the first sidewall of the gate stack and over the top surface of the fin;

a second gate spacer structure along the second sidewall of the gate stack, the second gate spacer structure comprising a second gate spacer, a first portion of the second gate spacer extending along the second sidewall of the gate stack, a second portion of the second gate spacer extending laterally away from the second sidewall of the gate stack and over the top surface of the fin, a width of the second portion of the second gate spacer being less than a width of the second portion of the first gate spacer;

a first epitaxial region adjacent the first gate spacer structure; and

a second epitaxial region adjacent the second gate spacer structure.

16. The device of claim 15, wherein the first gate spacer structure further comprises a third gate spacer extending along a sidewall of the first portion of the first gate spacer.

17. The device of claim 16, wherein the second gate spacer structure further comprises a fourth gate spacer extending along a sidewall of the first portion of the second gate spacer, a width of the fourth gate spacer being substantially equal to a width of the third gate spacer.

18. The device of claim 15, wherein a volume of the first epitaxial region is greater than a volume of the second epitaxial region.

19. The device of claim 15, wherein a width of the first epitaxial region is greater than a width of the second epitaxial region.

20. The device of claim 15, wherein a thickness of the first epitaxial region is greater than a thickness of the second epitaxial region.