Forming epitaxial structures in fin field effect transistors

• US 10,522,656 B2
• Filed: 02/28/2018
• Issued: 12/31/2019
• Est. Priority Date: 02/28/2018
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Chan, Chia-Ling, Chen, Derek, Chen, Liang-Yin, Kuo, Chien-I
• Primary Examiner(s): Kielin, Erik
• Application Number:
  US15/907,427
• Publication Number:
  US 20190267471A1
• Time in Patent Office: 671 Days
• Field of Search: None
• CPC Class Codes: H01L 21/02532 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/0257 Doping during depositing
• CPC Class Codes: H01L 21/0262 Reduction or decomposition of gaseous compounds, e.g. CVD
• CPC Class Codes: H01L 21/2252 using predeposition of impurities into the semiconductor surface, e.g. from a gaseous phase
• CPC Class Codes: H01L 21/324 Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering H01L21/20 - H01L21/288 and H01L21/302 - H01L21/322 take precedence
• CPC Class Codes: H01L 21/823814 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/823821 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/0924 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/167 further characterised by the doping material H01L29/1604 takes precedence
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66636 with source or drain recessed by etching or first recessed by etching and then refilled
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7851 with the body tied to the substrate

Abstract

A method of forming source/drain features in a FinFET device includes providing a fin formed over a substrate and a gate structure formed over a fin, forming a recess in the fin adjacent to the gate structure, forming a first epitaxial layer in the recess, forming a second epitaxial layer over the first epitaxial layer, and forming a third epitaxial layer over the second epitaxial layer. The second epitaxial layer may be doped with a first element, while one or both of the first and the third epitaxial layer includes a second element different from the first element. One or both of the first and the third epitaxial layer may be formed by a plasma deposition process.

Claims

1. A method, comprising:

forming a fin over a substrate;

forming a gate structure over the fin;

removing a portion of the fin adjacent to the gate structure to form a recess;

forming a source/drain feature in the recess, wherein forming the source/drain feature includes;

depositing a film including a first element in the recess, wherein the first element in a portion of the film penetrates bottom and sidewall surfaces of the recess to form a diffusion layer;

removing a top portion of the film to expose the bottom and sidewall surfaces of the recess;

thereafter, performing a first annealing process to the diffusion layer, thereby forming a first epitaxial layer;

forming a second epitaxial layer over the first epitaxial layer, such that the second epitaxial layer is in contact with the bottom and sidewall surfaces of the recess; and

forming a third epitaxial layer over the second epitaxial layer, wherein the second epitaxial layer and the third epitaxial layer include a second element different from the first element, and wherein both the first and the second elements are n-type dopants; and

performing a second annealing process to the source/drain feature.

2. The method of claim 1, wherein removing the top portion of the film includes exposing the film to a mixture of sulfuric acid and hydrogen peroxide at a temperature between about 150 degrees Celsius and about 180 degrees Celsius for a duration between about 30 seconds and about 65 seconds.

3. The method of claim 1, wherein performing the first annealing process is implemented at a temperature between about 900 degrees Celsius and about 1000 degrees Celsius for a duration between about 1 second and about 2 seconds.

4. The method of claim 1, wherein performing the second annealing process is implemented at a temperature between about 1000 degrees Celsius and about 1200 degrees Celsius for a duration of less than about 10 millisecond.

5. The method of claim 1, wherein depositing the film includes exposing the bottom and sidewall surfaces of the recess to a dose of plasma including the first element and a carrier gas, wherein the carrier gas includes hydrogen, helium, or a combination thereof.

6. The method of claim 5, wherein the first element is arsenic and the second element is phosphorous.

7. The method of claim 1, wherein forming the second epitaxial layer or the third epitaxial layer includes implementing an in-situ epitaxial process.

17. The method of claim 1, wherein removing the top portion of the film includes cleaning the film with a sulfuric acid and hydrogen peroxide mixture (SPM).

8. A method, comprising:

performing a first etching process to a top portion of a fin disposed over a semiconductor substrate, thereby forming a trench in the fin;

forming a material layer including a first element in the trench, wherein a portion of the material layer diffuses into the fin to form a buried layer below bottom and sidewall surfaces of the trench;

performing a second etching process to remove a top portion of the material layer that is over the buried layer;

subsequent to performing the second etching process, performing a first annealing treatment to the buried layer;

forming a first epitaxial semiconductor layer including a second element on the annealed buried layer, wherein the first element and the second element are of the same conductivity type, and wherein the first element is arsenic;

forming a second epitaxial semiconductor layer including the second element over the first epitaxial semiconductor layer; and

performing a second annealing treatment to the first and the second epitaxial semiconductor layers.

9. The method of claim 8, wherein forming the first and the second epitaxial semiconductor layers each includes forming a silicon-containing epitaxial semiconductor layer doped with phosphorus.

10. The method of claim 8, wherein forming the material layer includes implementing a plasma deposition process, and wherein forming the first or the second epitaxial semiconductor layer includes implementing a selective epitaxial growth process.

11. The method of claim 8, wherein forming the material layer includes implementing an atomic-layer deposition process, and wherein forming the first or the second epitaxial semiconductor layer includes implementing a selective epitaxial growth process.

12. The method of claim 8, wherein performing the second etching process includes treating the material layer with a cleaning mixture, and wherein the cleaning mixture includes sulfuric acid and hydrogen peroxide.

13. The method of claim 8, wherein the second annealing treatment is performed at a higher temperature than the first annealing treatment.

18. The method of claim 12, wherein treating the material layer with the cleaning mixture is implemented at a temperature of about 150 degrees Celsius to about 180 degrees Celsius.

14. A method, comprising:

recessing a semiconductor fin disposed over a substrate;

depositing a dopant-containing layer over the recessed semiconductor fin, wherein a first portion of the dopant-containing layer is embedded below bottom and sidewall surfaces of the recessed semiconductor fin, and wherein the dopant-containing layer includes a first dopant;

removing a second portion of the dopant-containing layer disposed over the first portion, thereby exposing the bottom and sidewall surfaces of the recessed semiconductor fin;

subsequent to removing the second portion, annealing the first portion of the dopant-containing layer;

subsequent to annealing the first portion, depositing a first epitaxial layer on the first portion of the dopant-containing layer;

depositing a second epitaxial layer over the first epitaxial layer to form a source/drain (S/D) feature, wherein the first and the second epitaxial layers include a second dopant different from the first dopant, wherein the second dopant is of the same conductivity type as the first dopant; and

annealing the first and the second epitaxial layers.

15. The method of claim 14, wherein annealing the first portion of the dopant-containing layer forms an epitaxial silicon-containing semiconductor layer doped with the first dopant.

16. The method of claim 14, wherein depositing the dopant-containing layer includes implementing a plasma deposition process, and wherein depositing the first or the second epitaxial layer includes implementing an in-situ epitaxial process.

19. The method of claim 14, wherein the first dopant is arsenic, and wherein the second dopant is phosphorous.

20. The method of claim 14, wherein depositing the first epitaxial layer results in the first epitaxial layer having a first concentration of the second dopant, wherein depositing the second epitaxial layer results in the second epitaxial layer having a second concentration of the second dopant, and wherein the first concentration is higher than the second concentration.