Integrated circuit including field effect transistor structures with gate and field electrodes and methods for manufacturing and operating an integrated circuit

• US 10,522,675 B2
• Filed: 01/25/2012
• Issued: 12/31/2019
• Est. Priority Date: 01/25/2012
• Status: Active Grant

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Kadow, Christoph
• Primary Examiner(s): Gondarenko, Natalia A
• Application Number:
  US13/358,272
• Publication Number:
  US 20130187196A1
• Time in Patent Office: 2,897 Days
• Field of Search: 257140, 257337, 257341, 257E2706, 257E29197, 257334
• CPC Class Codes: H01L 21/823487 with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface with a current flow parallel to the substrate surface H01L21/823431
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 29/0615 by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] LDD or drain offset regions H01L29/7833
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/7803 structurally associated with at least one other device assemblies H01L25/00; integrated circuits H01L27/00
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

An integrated circuit includes a first and a second field effect transistor structure. The first field effect transistor structure includes a first gate electrode structure and a first field electrode structure. The second field effect transistor structure includes a second gate electrode structure and a second field electrode structure. The first and the second gate electrode structures are electrically separated from each other. The first and the second field electrode structures are separated from each other.

Claims

1. A method of manufacturing an integrated circuit, the method comprising:

forming, in a semiconductor die, at least one of a logic circuit and a driver circuit;

forming, in the semiconductor die, a first field effect transistor structure comprising a first gate electrode structure, a first field electrode structure, a first channel region of a second conductivity type, and a first drain zone section of a first conductivity type opposite the second conductivity type, and

forming, in the semiconductor die, a second field effect transistor structure comprising a second gate electrode structure, a second field electrode structure, a second channel region of the second conductivity type, and a second drain zone section of the first conductivity type,

wherein

the first gate electrode structure and the second gate electrode structure are formed to be electrically separated from each other,

the first field electrode structure and the second field electrode structure are formed to be electrically separated from each other,

the first drain zone section and the second drain zone section form a contiguous drain zone of the first conductivity type in the semiconductor die,

the second field electrode structure is electrically connected to the second gate electrode structure, to increase a gate-to-drain capacitance of the second field effect transistor structure,

the first field electrode structure is electrically coupled to a source electrode of the first field effect transistor structure, to lower a gate-to-drain capacitance of the first field effect transistor structure,

the first field effect transistor structure is a power switch configured to switch a load to a power supply and control a load current, and

the second field effect transistor structure is a protection switch configured to respond to fast transient impulses and thereby protect the integrated circuit from destructive currents.

2. The method of claim 1, wherein

the first field effect transistor structure is formed in a first active area of the integrated circuit, and

the second field effect transistor structure is formed in a second active area of the integrated circuit, and further comprising

providing an isolation structure between the first active area and the second active area.

3. The method of claim 1, wherein

the second field effect transistor structure comprises a source electrode, and

the source electrode of the first field effect transistor structure and the source electrode of the second field effect transistor structure are electrically separated from each other.

4. The method of claim 1, further comprising:

electrically coupling the source electrode of the first field effect transistor structure to a first source terminal of the integrated circuit.

5. The method of claim 4, further comprising:

electrically coupling a source electrode of the second field effect transistor structure to a second source terminal of the integrated circuit.

6. The method of claim 1, wherein

forming the first field effect transistor structure comprises forming the first field effect transistor structure in a first active area of the integrated circuit, and

forming the second field effect transistor structure comprises forming the second field effect transistor structure in a second active area of the integrated circuit, and

the method further comprises electrically separating the first active area and the second active area by two pn-junctions.

7. The method of claim 1, further comprising:

electrically coupling the contiguous drain zone to a drain terminal of the integrated circuit.

8. The method of claim 1, further comprising:

electrically coupling a first driver circuit to the second gate electrode structure, the first driver circuit configured to control a potential at the second gate electrode structure.

9. The method of claim 1, further comprising:

electrically coupling a second driver circuit to the second field electrode structure, the second driver circuit configured to control a potential at the second field electrode structure.

10. The method of claim 1, further comprising:

electrically coupling a first driver circuit to the second gate electrode structure, the first driver circuit configured to control a potential at the second gate electrode structure;

electrically coupling a second driver circuit to the second field electrode structure, the second driver circuit configured to control a potential at the second field electrode structure; and

providing a logic circuit configured to control the first driver circuit and the second driver circuit.

11. The method of claim 1, further comprising:

electrically coupling a third driver circuit to the first gate electrode structure.

12. The method of claim 1, wherein

forming the first field effect transistor structure comprises forming first source regions adjoining to a first surface of the semiconductor die, the first drain zone section being formed within the semiconductor die at a distance to the first source regions and in a vertical projection of the first source regions, and

forming the second field effect transistor structure comprises forming second source regions adjoining to the first surface of the semiconductor die, the second drain zone section being formed within the semiconductor die at a distance to the second source regions and in a vertical projection of the second source regions.

13. The method of claim 12, wherein forming the first drain zone section and the second drain zone section comprises:

forming the first drain zone section and the second drain zone section at a second surface of the semiconductor die; and

electrically coupling the first drain zone section and the second drain zone section to a drain terminal of the integrated circuit.

14. The method of claim 12, further comprising:

forming a collector layer directly adjoining to the first drain zone section and the second drain zone section at a second surface of the semiconductor die; and

electrically coupling the collector layer to a collector terminal of the integrated circuit.

15. The method of claim 1, wherein

forming the first gate electrode structure and the first field electrode structure comprises forming the first gate electrode structure and the first field electrode structure in at least one first trench structure extending from a first surface into the semiconductor die, and

forming the second gate electrode structure and the second field electrode structure comprises forming the second gate electrode structure and the second field electrode structure in at least one second trench structure extending from the first surface into the semiconductor die.

16. The method of claim 15, wherein in each of the at least one first trench structure and the at least one second trench structure, a respective gate electrode structure is formed in a first trench portion oriented to the first surface and at least a part of a respective field electrode structure is formed in a second trench portion oriented to a bottom of a respective trench structure.

17. The method of claim 15, wherein the at least one first trench structure and the at least one second trench structure have a same shape and a same size.

18. An integrated circuit, comprising:

at least one of a logic circuit and a driver circuit formed in a semiconductor die;

a first field effect transistor structure formed in the semiconductor die, the first field effect transistor structure comprising a first gate electrode structure, a first field electrode structure, a first channel region of a second conductivity type, and a first drain zone section of a first conductivity type opposite the second conductivity type; and

a second field effect transistor structure formed in the semiconductor die, the second field effect transistor structure comprising a second gate electrode structure, a second field electrode structure, a second channel region of the second conductivity type, and a second drain zone section of the first conductivity type,

wherein the first gate electrode structure and the second gate electrode structure are electrically separated from each other,

wherein the first field electrode structure and the second field electrode structure are electrically separated from each other,

wherein the first and second drain zone sections the first drain zone section and the second drain zone section form a contiguous drain zone of the first conductivity type in the semiconductor die,

wherein the second field electrode structure is electrically connected to the second gate electrode structure, to increase a gate-to-drain capacitance of the second field effect transistor structure,

wherein the first field electrode structure is electrically coupled to a source electrode of the first field effect transistor structure, to lower a gate-to-drain capacitance of the first field effect transistor structure,

wherein the first field effect transistor structure is a power switch configured to switch a load to a power supply and control a load current,

wherein the second field effect transistor structure is a protection switch configured to respond to fast transient impulses and thereby protect the integrated circuit from destructive currents.

19. The integrated circuit of claim 18, further comprising:

a first source terminal; and

a second source terminal,

wherein the source electrode of the first field effect transistor structure is electrically coupled to the first source terminal,

wherein the source electrode of the second field effect transistor structure is electrically coupled to the second source terminal.