Semiconductor device and method of manufacturing semiconductor device

• US 10,522,676 B2
• Filed: 12/14/2018
• Issued: 12/31/2019
• Est. Priority Date: 09/14/2016
• Status: Active Grant

• Current Assignee: Fuji Electric Company Limited (Fuji Electric Systems Company Limited)
• Original Assignee: Fuji Electric Company Limited (Fuji Electric Systems Company Limited)
• Inventors: Kinoshita, Akimasa
• Primary Examiner(s): Sefer, Ahmed N
• Application Number:
  US16/221,272
• Publication Number:
  US 20190131449A1
• Time in Patent Office: 382 Days
• CPC Class Codes: H01L 21/046 using ion implantation
• CPC Class Codes: H01L 29/045 by their particular orientation of crystalline planes
• CPC Class Codes: H01L 29/0623 Buried supplementary region, e.g. buried guard ring multi-RESURF H01L29/0634
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/1608 Silicon carbide
• CPC Class Codes: H01L 29/66068 the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A MOS gate having a trench gate structure is formed on the front surface side of a silicon carbide substrate. A gate trench of the trench gate structure goes through an n⁺ source region and a p-type base region and reaches an n⁻ drift region. Between adjacent gate trenches, a first p⁺ region that goes through the p-type base region in the depth direction and reaches the n⁻ drift region is formed at a position separated from the gate trenches. The first p⁺ region is formed directly beneath a p⁺⁺ contact region. The width of the first p⁺ region is less than the width w1 of the gate trench. A second p⁺ region is formed at the bottom of the gate trench. The first and second p⁺ regions are silicon carbide epitaxial layers.

Claims

1. A semiconductor device, comprising:

a semiconductor substrate made of a semiconductor having a wider bandgap than silicon;

a first semiconductor layer of a first conductivity type formed on a front surface of the semiconductor substrate;

a second semiconductor layer of a second conductivity type formed on a surface of the first semiconductor layer on a side opposite to the semiconductor substrate;

a first semiconductor region of the first conductivity type selectively formed within the second semiconductor layer;

a trench that goes through the first semiconductor region and the second semiconductor layer in a depth direction and reaches the first semiconductor layer;

a gate electrode formed within the trench with a gate insulating film interposed between the gate electrode and an inner surface of the trench;

a second semiconductor region of the second conductivity type that is formed separated and laterally isolated from the trench, penetrates through and across the second semiconductor layer in the depth direction and reaches the first semiconductor layer so that a bottom of the second semiconductor region is embedded in the first semiconductor layer, the second semiconductor region having a greater impurity concentration than the second semiconductor layer;

a third semiconductor region of the second conductivity type that is formed within the first semiconductor layer separated from the second semiconductor layer and the second semiconductor region, covers a bottom of the trench, and has a greater impurity concentration than the second semiconductor layer;

a first electrode that is electrically connected to the first semiconductor region and the second semiconductor layer;

a second electrode formed on a rear surface of the semiconductor substrate; and

a fourth semiconductor region of the second conductivity type that is selectively formed within the second semiconductor layer and has a greater impurity concentration than the second semiconductor region,

wherein the first electrode contacts the first semiconductor region and the fourth semiconductor region, and

wherein the second semiconductor region is formed on a side of the fourth semiconductor region facing the second electrode and contacts the fourth semiconductor region.

2. The semiconductor device according to claim 1, wherein a width of the second semiconductor region is less than a width of the trench.

3. The semiconductor device according to claim 1, wherein the bottom of the second semiconductor region facing the second electrode is positioned closer to the second electrode in depth than the bottom of the trench.

4. The semiconductor device according to claim 1, wherein the second semiconductor region is an epitaxial layer.

5. The semiconductor device according to claim 1, wherein the third semiconductor region is an epitaxial layer.

6. The semiconductor device according to claim 1, wherein the semiconductor having a wider bandgap than silicon is silicon carbide.

7. The semiconductor device according to claim 1,

wherein a surface of the second semiconductor layer on a side opposite to the first semiconductor layer is a (0001) plane, and

wherein sidewalls of the trench are {1-100 } planes.

8. The semiconductor device according to claim 1, wherein the second semiconductor layer has a second conductivity type impurity concentration profile that exhibits a Gaussian distribution with differing impurity concentrations from high to low in the depth direction from a position that has a highest impurity concentration.

9. A semiconductor device, comprising:

a semiconductor substrate made of a semiconductor having a wider bandgap than silicon;

a first semiconductor layer of a first conductivity type formed on a front surface of the semiconductor substrate;

a second semiconductor layer of a second conductivity type formed on a surface of the first semiconductor layer on a side opposite to the semiconductor substrate;

a first semiconductor region of the first conductivity type selectively formed within the second semiconductor layer;

a trench that goes through the first semiconductor region and the second semiconductor layer in a depth direction and reaches the first semiconductor layer;

a gate electrode formed within the trench with a gate insulating film interposed between the gate electrode and an inner surface of the trench;

a second semiconductor region of the second conductivity type that is formed separated and laterally isolated from the trench, penetrates through and across the second semiconductor layer in the depth direction and reaches the first semiconductor layer so that a bottom of the second semiconductor region is embedded in the first semiconductor layer, the second semiconductor region having a greater impurity concentration than the second semiconductor layer;

a third semiconductor region of the second conductivity type that is formed within the first semiconductor layer separated from the second semiconductor layer and the second semiconductor region, covers a bottom of the trench, and has a greater impurity concentration than the second semiconductor layer;

a first electrode that is electrically connected to the first semiconductor region and the second semiconductor layer;

a second electrode formed on a rear surface of the semiconductor substrate; and

a fourth semiconductor region of the second conductivity type formed within the first semiconductor layer on a side of the second semiconductor region facing the second electrode.

10. The semiconductor device according to claim 9, further comprising:

a fifth semiconductor region of the second conductivity type that is selectively formed within the second semiconductor layer and has a greater impurity concentration than the second semiconductor region,

wherein the first electrode contacts the first semiconductor region and the fifth semiconductor region, and

wherein the second semiconductor region is formed on a side of the fifth semiconductor region facing the second electrode and contacts the fifth semiconductor region.

11. The semiconductor device according to claim 9, wherein a width of the fourth semiconductor region is greater than the width of the second semiconductor region.

12. The semiconductor device according to claim 9, wherein the fourth semiconductor region covers the bottom of the second semiconductor region facing the second electrode.

13. The semiconductor device according to claim 9,

wherein the trench is formed in a linear layout that extends parallel to the front surface of the semiconductor substrate, and

wherein the second semiconductor region and the fourth semiconductor region are formed in linear layouts parallel to a direction in which the trench linearly extends.

14. The semiconductor device according to claim 9,

wherein the trench is formed in a linear layout that extends parallel to the front surface of the semiconductor substrate,

wherein the second semiconductor region is formed in a linear layout parallel to a direction in which the trench linearly extends, and

wherein the fourth semiconductor region is arranged in a plurality at a prescribed interval in a direction in which the second semiconductor region linearly extends.

15. The semiconductor device according to claim 9, wherein an impurity concentration of the fourth semiconductor region is greater than the impurity concentration of the second semiconductor region.

16. The semiconductor device according to claim 9, wherein a width of the second semiconductor region is less than a width of the trench.

17. The semiconductor device according to claim 9, wherein the bottom of the second semiconductor region facing the second electrode is positioned closer to the second electrode in depth than the bottom of the trench.

18. The semiconductor device according to claim 9, wherein the second semiconductor layer has a second conductivity type impurity concentration profile that exhibits a Gaussian distribution with differing impurity concentrations from high to low in the depth direction from a position that has a highest impurity concentration.

19. A semiconductor device, comprising:

a semiconductor substrate made of a semiconductor having a wider bandgap than silicon;

a first semiconductor layer of a first conductivity type formed on a front surface of the semiconductor substrate;

a second semiconductor layer of a second conductivity type formed on a surface of the first semiconductor layer on a side opposite to the semiconductor substrate;

a first semiconductor region of the first conductivity type selectively formed within the second semiconductor layer;

a trench that goes through the first semiconductor region and the second semiconductor layer in a depth direction and reaches the first semiconductor layer;

a gate electrode formed within the trench with a gate insulating film interposed between the gate electrode and an inner surface of the trench;

a second semiconductor region of the second conductivity type that is formed separated and laterally isolated from the trench, penetrates through and across the second semiconductor layer in the depth direction and reaches the first semiconductor layer so that a bottom of the second semiconductor region is embedded in the first semiconductor layer, the second semiconductor region having a greater impurity concentration than the second semiconductor layer;

a third semiconductor region of the second conductivity type that is formed within the first semiconductor layer separated from the second semiconductor layer and the second semiconductor region, covers a bottom of the trench, and has a greater impurity concentration than the second semiconductor layer;

a first electrode that is electrically connected to the first semiconductor region and the second semiconductor layer; and

a second electrode formed on a rear surface of the semiconductor substrate,

wherein the second semiconductor layer has a second conductivity type impurity concentration profile that exhibits a Gaussian distribution with differing impurity concentrations from high to low in the depth direction from a position that has a highest impurity concentration.

20. The semiconductor device according to claim 19, wherein a width of the second semiconductor region is less than a width of the trench.

21. The semiconductor device according to claim 19, wherein the bottom of the second semiconductor region facing the second electrode is positioned closer to the second electrode in depth than the bottom of the trench.